- 21 Sep, 2021 1 commit
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Add model parameter to enable loading of mcp_ramfw.bin file at the address 0x0BF80000. Signed-off-by:Shriram K <shriram.k@arm.com> Change-Id: If305a95abe4e3e71811b311ec7b2bd6fe26c39f2
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- 16 Sep, 2021 2 commits
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Allow UEFI SCT tests to be executed on additional platforms. This allows executing the UEFI SCT tests as an independent test outside of ACS test suite. Independent tests allows for selecting the tests to be executed. Signed-off-by:Zakaria Zahi <zakaria.zahi@arm.com> Change-Id: Ib004c2c4cfe7844891a453eba37b3806ec41f83f
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Enabling PCIe ACS parameters on root ports are causing SMMU test engines, connected on these root ports, to go to same IOMMU translation group. This is causing misconfiguration of MSIs in kvmtool for these devices when trying to boot VMs with PCI-passthrough I/O virtualized devices. Therefore, adding these parameters is currently defeating the purpose of having separate devices for VFIO based virtualization testing. These parameters are required to support SBSA PCIe exerciser test cases. At present the support for PCI MSI is not enabled in GIC from UEFI and hence the exerciser test cases are skipped. These parameters should be added back after MSI support is enabled. Change-Id: I1c99d62dbdb7f89629929b89da85214cdccab54b Signed-off-by:Pranav Madhu <pranav.madhu@arm.com>
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- 14 Sep, 2021 7 commits
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Vijayenthiran Subramaniam authored
Add initial model startup support for RD-N2-Cfg2 platform. This supports busybox and distro boot tests. Signed-off-by:Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: Idb28b387dc00bb9ff22dbeb105a956540e4abd0e
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Add PCIe switch configuration for RD-N2-Cfg1 platform to support SBSA PCI test cases. Signed-off-by: -
Add PCIe switch configuration for RD-N2 platform to support SBSA PCI test cases. Signed-off-by: -
Add PCIe switch configuration for RD-V1 platform to support SBSA PCI test cases. Signed-off-by: -
Add model parameter to enable loading of mcp_ramfw.bin file at the address 0x0BF80000. Signed-off-by: -
Add model parameter to enable loading of mcp_ramfw.bin file at the address 0x0BF80000. Signed-off-by: -
Add model parameter to enable loading of mcp_ramfw.bin file at the address 0x0BF80000. Signed-off-by:
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- 11 Aug, 2021 2 commits
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Configure PL330 DMA controllers behind the non-pcie io macro for non-secure mode at boot reset. Signed-off-by:Vivek Gautam <vivek.gautam@arm.com> Change-Id: Ib172537accb57beba7081ee83e651dc060ceb072
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Configure PL330 DMA controllers behind the non-pcie io macro for non-secure mode at boot reset. Signed-off-by:
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- 10 Aug, 2021 16 commits
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Vijayenthiran Subramaniam authored
Replace all instances of exercisers with SMMU v3 test engines. Signed-off-by: -
Vijayenthiran Subramaniam authored
Minimal endpoint json file was passed to the pcie root complex on which the software enumeration will not be done. With 11.15 FVP, if the json file is not passed to a pcie root complex, the pcie hierarchy will not be created. So minimal endpoint json file is not used anymore. This patch removes the stale file. Signed-off-by: -
Vijayenthiran Subramaniam authored
Prior to FVP version 11.15, FVP will create default pcie hierarchy if a json hierarchy file is not passed to pciex* root complex. Creating default hierarchy on all the ports slowed down the launch of the model. To avoid this, a minimal end point topology file is passed to speed up the launch of the model. With 11.15, FVP will not create any pcie hierarchy if a topology file is not passed to pciex*. Hence passing the minimal end point topology file is not required anymore. Signed-off-by: -
Vijayenthiran Subramaniam authored
Prior to FVP version 11.15, FVP will create default pcie hierarchy if a json hierarchy file is not passed to pciex* root complex. Creating default hierarchy on all the ports slowed down the launch of the model. To avoid this, a minimal end point topology file is passed to speed up the launch of the model. With 11.15, FVP will not create any pcie hierarchy if a topology file is not passed to pciex*. Hence passing the minimal end point topology file is not required anymore. Signed-off-by: -
Vijayenthiran Subramaniam authored
Before 11.15, if any hierarchy file is not passed to pcie_group_* port, default pcie topology will be created. Starting from 11.15, if no file is passed, FVP will not create any pcie hierarchy. To create FVP's default pcie hierarchy corresponding port has to be set to <default>. On both RD-N2, IO macro 0's x16 is used to create default pcie hierarchy. Signed-off-by: -
Vijayenthiran Subramaniam authored
Before 11.15, if any hierarchy file is not passed to pcie_group_* port, default pcie topology will be created. Starting from 11.15, if no file is passed, FVP will not create any pcie hierarchy. To create FVP's default pcie hierarchy corresponding port has to be set to <default>. On both RD-N2-Cfg1, IO macro 0's x16 is used to create default pcie hierarchy. Signed-off-by: -
Vijayenthiran Subramaniam authored
PCIe root complexes are removed from IO macro 4 and it has been populated with non-pcie devices and hence pcie_group_4 model param has been retired. Signed-off-by: -
Vijayenthiran Subramaniam authored
Example pcie hierarchy 1 was passed to io macro 1 to create a pcie hierarchy. With 11.15 model, non-pcie devices are connected to io macro 1. So removed the example file. Signed-off-by: -
Vijayenthiran Subramaniam authored
PCIe root complexes are removed from IO macro 1 and it has been populated with non-pcie devices and hence pcie_group_1 model param has been retired. Signed-off-by: -
Vijayenthiran Subramaniam authored
From FVP version 11.15 onward, pcie_rc namespace has been removed from pcie_group_* for which hierarchy file is passed. Update run_model.sh scripts to remove pcie_rc param. Signed-off-by: -
Vijayenthiran Subramaniam authored
From FVP version 11.15 onward, pcie_rc namespace has been removed from pcie_group_* for which hierarchy file is passed. Update run_model.sh scripts to remove pcie_rc param. Signed-off-by: -
Vijayenthiran Subramaniam authored
With 11.15 version of RD-N2 FVP, all instances of the parameter io_macro_* has been renamed to pcie_group_*. Update the model parameters accordingly in the run_model script. Signed-off-by: -
Vijayenthiran Subramaniam authored
With 11.15 version of RD-N2-Cfg1 FVP, all instances of the parameter io_macro_* has been renamed to pcie_group_*. Update the model parameters accordingly in the run_model script. Signed-off-by: -
Vijayenthiran Subramaniam authored
Add model parameter to enable loading of mcp_ramfw.bin file at the address 0x0BF80000. Signed-off-by: -
For RD-N2 and RD-N2-Cfg1 platforms, add model parameter to enable loading of mcp_ramfw.bin file at the address 0x0BF80000. Signed-off-by: -
Vijayenthiran Subramaniam authored
RD-N2-Cfg1 platform supports booting buildroot filesystem. Enable booting buildroot filesystem for rdn2cfg1. Signed-off-by:
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- 26 May, 2021 1 commit
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Vijayenthiran Subramaniam authored
In order to keep the pcie hierarchy file specific to rdn2 and rdn2cfg1 platforms, create the example pcie hierarchy file within the each platform folders. Signed-off-by:
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- 25 May, 2021 1 commit
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Vijayenthiran Subramaniam authored
In order to support pcie hierarchy which start with non-zero bus number, ecam_start_bus_number parameter through hierarchy json file has been added to the FVP. Set this parameter for all hierarchy with 32 bus offset each. Signed-off-by:
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- 30 Apr, 2021 6 commits
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Instantiate example PCIe hierarchy file under IO Macro 1's pciex16 port to enable support for multiple IO Macros. Corresponding software changes are required to enumerate the devices attached to multiple IO Macros. Signed-off-by: -
In preparation to enable support for multiple IO Macros (on pciex16), attach the minimal endpoint topology file to io_macro_0.pciex4_0 and don't pass any topology file to io_macro_0.pciex16. By not passing any topology file, FVP will create a default predefined PCIe topology with multiple exercisers, switches, smmu test engines and ahci devices. Also, update the ahci image path to use io_macro_0.pciex16 instead of io_macro_0.pciex4. Signed-off-by: -
Instantiate example PCIe hierarchy file under IO Macro 1..4's pciex16 port to enable support for multiple IO Macros. Corresponding software changes are required to enumerate the devices attached to multiple IO Macros. Signed-off-by: -
In preparation to enable support for multiple IO Macros (on pciex16), attach the minimal endpoint topology file to io_macro_0.pciex4_0 and don't pass any topology file to io_macro_0.pciex16. By not passing any topology file, FVP will create a default predefined PCIe topology with multiple exercisers, switches, smmu test engines and ahci devices. Also, update the ahci image path to use io_macro_0.pciex16 instead of io_macro_0.pciex4. Signed-off-by: -
RD-N2 and RD-N2-Cfg1 FVPs has multiple IO Macros and each IO Macro have four PCIe root buses (x16, x8, x4_1, x4_0). These FVPs accepts custom PCIe topology file and instantiates the PCIe topology as represented in the topology file. Add example PCIe hierarchy files to be instantiated under root buses. Each topology is configured to have 32 MiB ECAM space (thus 32 possible buses), 64 MiB MMIOL and 32 GiB MMIOH space. Signed-off-by: -
${TOPOLOGY_FILE points} to a minimal pcie topology file with a single end point device (exerciser). Rename this variable to ${MINIMAL_EP_TOPOLOGY_FILE} to indicate that it is pointing to a minimal topology file. Signed-off-by:
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- 25 Mar, 2021 1 commit
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Add initial model startup support for RD-N2 Cfg1 platform. This supports busybox, distro boot, secure boot and acs tests. Signed-off-by:Aditya Angadi <aditya.angadi@arm.com> Change-Id: Ifdd437a826472ba5c35f5f207b95fa7ccd67ad06
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- 23 Mar, 2021 3 commits
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RD-N2 FVP has been update to use IO Macro for the PCIe root complex. The initial support has been added such that one IO Macro is enabled out of the five IO Macros. Use the PCIe topology behind this IO Macro for passing the achi sata disk image. Also for the root ports which are not used by the software, pass the minimal PCIe hierarchy file to speed up the launch of FVP. Signed-off-by: -
Add a minimal pcie hierarchy file with exerciser as endpoint for the use of latest RD platforms. Signed-off-by: -
FVP_RD_Daniel_4XLR has been renamed to FVP_RD_V1_Multichip since the platform is based on Neoverse V1. Update the error message to use the updated FVP name. Signed-off-by:
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