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FVP_RD_N2_Multichip has been renamed to FVP_RD_N2_Cfg2 starting from
11.16/25 version. Update the warning message accordingly.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Ie29daa30ec7c58609c00f65c230a32bf568513d0

RD-N2-Cfg2 platform has four TZCs (0-3) on each chip. Remove additional
four TZCs (4-7) that were programmed to bypass on each chip.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I82459dd75b6a972baaf6811545823a2b884303dc

shriram-k-arm authored Nov 26, 2021 and Vijayenthiran Subramaniam committed Nov 26, 2021

Replace the term "u-root" with "busybox" in the comments since booting
of stage-2 kernel with busybox prompt is automated. Also update the
disclaimer message, since we no longer boot stage-1 linux kernel by
replacing the UEFI Shell binary.
Signed-off-by: Shriram K <shriram.k@arm.com>
Change-Id: I2a3126f127ad67aca6be6906881b4acd6761235f

FVP by default blocks all the transaction if trustzone controller (TZC)
is not configured by software. This is an opposite behaviour to hardware
which allows all access if the TZC is not configured by software. To
align with hardware behaviour, use model parameters to configure TZC to
be bypassed and allow all access until software reconfigures the TZC.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Id8e4f5160df2655ee29fc182ba29b46fdd6e31e9

FVP by default blocks all the transaction if trustzone controller (TZC)
is not configured by software. This is an opposite behaviour to hardware
which allows all access if the TZC is not configured by software. To
align with hardware behaviour, use model parameters to configure TZC to
be bypassed and allow all access until software reconfigures the TZC.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I4f5c22bce7fb1f6067c394db21b5329a439dd666

FVP by default blocks all the transaction if trustzone controller (TZC)
is not configured by software. This is an opposite behaviour to hardware
which allows all access if the TZC is not configured by software. To
align with hardware behaviour, use model parameters to configure TZC to
be bypassed and allow all access until software reconfigures the TZC.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I6ee4dc2c45cca786ec178ec7403f3b161cd2417f

FVP by default blocks all the transaction if trustzone controller (TZC)
is not configured by software. This is an opposite behaviour to hardware
which allows all access if the TZC is not configured by software. To
align with hardware behaviour, use model parameters to configure TZC to
be bypassed and allow all access until software reconfigures the TZC.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Icae0f6fe9ad9e48cdfa173a55b82e81d81b7e54c

FVP by default blocks all the transaction if trustzone controller (TZC)
is not configured by software. This is an opposite behaviour to hardware
which allows all access if the TZC is not configured by software. To
align with hardware behaviour, use model parameters to configure TZC to
be bypassed and allow all access until software reconfigures the TZC.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I2ea2a29432b04b5fc9418f4480e97d6e266335b7

Until 11.15 version, RD-N2-Cfg2 FVP had `mem` component which
instantiated `n` number of TZC's statistically and controlled the access
to number of regions required for a particular TZC during runtime.
Starting from 11.16 version, the `mem` component is removed and the
number of regions parameter (`tzcN.num_region`) for a particular TZC has
been removed as a model parameter and is configured statically by the
model.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I7def859a4ff1df1dc83f7a17e07086aa823737e4

Until 11.15 version, RD-Edmunds FVP had `mem` component which
instantiated `n` number of TZC's statistically and controlled the access
to number of regions required for a particular TZC during runtime.
Starting from 11.16 version, the `mem` component is removed and the
number of regions parameter (`tzcN.num_region`) for a particular TZC has
been removed as a model parameter and is configured statically by the
model.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Id404803404ee2b834609b9ad9c395faf89b43c99

Until 11.15 version, RD-N2-Cfg1 FVP had `mem` component which
instantiated `n` number of TZC's statistically and controlled the access
to number of regions required for a particular TZC during runtime.
Starting from 11.16 version, the `mem` component is removed and the
number of regions parameter (`tzcN.num_region`) for a particular TZC has
been removed as a model parameter and is configured statically by the
model.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I3afb7e3ffe823a83621683962efb3d1c18f6f356

Until 11.15 version, RD-N2 FVP had `mem` component which instantiated
`n` number of TZC's statistically and controlled the access to number of
regions required for a particular TZC during runtime. Starting from
11.16 version, the `mem` component is removed and the number of regions
parameter (`tzcN.num_region`) for a particular TZC has been removed as a
model parameter and is configured statically by the model.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Ic92a94873dd3ea3546b9b8a725e8ce327742f7bc

Until 11.15 version, RD-V1 FVP had `mem` component which instantiated
`n` number of TZC's statistically and controlled the access to number of
regions required for a particular TZC during runtime. Starting from
11.16 version, the `mem` component is removed and the number of regions
parameter (`tzcN.num_region`) for a particular TZC has been removed as a
model parameter and is configured statically by the model.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: If367ce0c00c7755d8e846789d3807dcc426a29dc

Enable linuxboot test for RD-Edmunds platform.

This is an initial implementation of linuxboot for RD-Edmunds platform
and not the final version.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I344d1adbb5306b8c430e8f456d775046d3c9a392

shriram-k-arm authored Sep 27, 2021 and Vijayenthiran Subramaniam committed Oct 28, 2021

Enable linuxboot test for RD-N2-CFG1 platform.

This is an initial implementation of linuxboot for RD-N2-CFG1 Platform
and not the final version.
Signed-off-by: Shriram K <shriram.k@arm.com>
Change-Id: I91c2e0360a1aab7bb0c916ce0afd5e31b72da038

shriram-k-arm authored Sep 23, 2021 and Vijayenthiran Subramaniam committed Oct 28, 2021

Enable linuxboot test for RD-N2 platform.

This is an initial implementation of linuxboot for RD-N2 Platform and
not the final version.
Signed-off-by: Shriram K <shriram.k@arm.com>
Change-Id: I3f44c87498280d28dfb9bf24496e93e12421310c

shriram-k-arm authored Sep 08, 2021 and Vijayenthiran Subramaniam committed Oct 28, 2021

Enable linuxboot test for RD-V1 platform.

This is an initial implementation of linuxboot for RD-V1 platform and
not the final version.
Signed-off-by: Shriram K <shriram.k@arm.com>
Change-Id: Id4ee050fea1ccb671b9fbdc44f1baccb6e9d713f

shriram-k-arm authored Sep 08, 2021 and Vijayenthiran Subramaniam committed Oct 28, 2021

Add a run script for testing linuxboot on RD Platforms. This script
launches the FVP with an attached satadisk image that contains the
stage-2 linux kernel and busybox ramdisk image.

This is an initial implementation of linuxboot for RD Platforms and not
the final version.
Signed-off-by: Shriram K <shriram.k@arm.com>
Change-Id: I7209ae2fa1a99fc670f281eafedf2a9791c0fd09

tonykn-arm authored Aug 12, 2021 and Vijayenthiran Subramaniam committed Oct 27, 2021

Add initial model startup support for RD-Edmunds platform. This supports
busybox, buildroot, distro boot, secure boot and acs tests.
Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I3e2698acb63dd0a68f9af25c4cd7b4c2cb222028

Refactor RD-N2-Cfg2's run_model.sh script to print the full path of
Chip-0's UART logs and the full model launch command.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Ie96ac5fbae1c96b6f26caa1a086088156a313ed9

Refactor RD-N2-Cfg1's run_model.sh script to print the full path of all
the UART logs and the full model launch command.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Id8930fc9ce6a5708f91c60e060204214781ce815

Refactor RD-N2's run_model.sh script to print the full path of all the
UART logs and the full model launch command.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: If9c5a8883611c66725ab8de57144e8c9bf044fef

Refactor RD-V1-MC's run_model.sh script to print the full path of
Chip-0's UART logs and the full model launch command.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Ied07518d0e3e14f282ac6df87153473c0a2345a2

Refactor RD-V1's run_model.sh script to print the full path of all the
UART logs and the full model launch command.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I66a22594a0715ae1e3cd7a819bc6094505609d13

Refactor RD-N1-Edge-X2's run_model.sh script to print the full path of
Chip-0's UART logs and the full model launch command.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Id43cadf061942b85bb46e40218d1f1e679da1615

Refactor RD-E1-Edge's run_model.sh script to print the full path of all
the UART logs and the full model launch command.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I3839b083239ce5f56c9f10e1088500b7634e6a54

Refactor RD-N1-Edge's run_model.sh script to print the full path of all
the UART logs and the full model launch command.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I858a82d7b7836d58f1bcfcbbda777dece26c592e

Refactor SGI-575's run_model.sh script to print the full path of all the
UART logs and the full model launch command.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I4f4cf48e378f6ec0ca32e2f31f670c345b3d9d3d

MCP firmware uses css uart in MCP address space rather than soc uart on
all chips (css0..3). Fix the MCP's uart out file to use css uart.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I3c11dc83f6004a25050cb0d9dbaafddf96b5225b

MCP firmware uses css uart in MCP address space rather than soc uart.
Fix the MCP's uart out file to use css uart.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I57788f0c439089fc583c6eb0ac701dfac1e4e434

MCP firmware uses css uart in MCP address space rather than soc uart.
Fix the MCP's uart out file to use css uart.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Ie35067855cb373c429ea38b967069d47ebeb8f75

MCP firmware uses css uart in MCP address space rather than soc uart on
all chips (css0..3). Fix the MCP's uart out file to use css uart.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I5856b60b27363b29ecd931d7809175e563fae519

MCP firmware uses css uart in MCP address space rather than soc uart.
Fix the MCP's uart out file to use css uart.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I259cbedc2f30a109f166fc27a5294563d669bd48

MCP firmware uses css uart in MCP address space rather than soc uart on
both chips (css0 and css1). Fix the MCP's uart out file to use css uart.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I88717731d7f57de28b0c9429bcd59a117aa90315

MCP firmware uses css uart in MCP address space rather than soc uart.
Fix the MCP's uart out file to use css uart.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I592c1a0b40b86b62386149c22d71235469c6624f

MCP firmware uses css uart in MCP address space rather than soc uart.
Fix the MCP's uart out file to use css uart.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I272204cbb8eea165e712316d405d3633fa2bf2ec

MCP firmware uses css uart in MCP address space rather than soc uart.
Fix the MCP's uart out file to use css uart.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Id9b26de7349e5303e6abb64df5ee4a4babb7d860

shriram-k-arm authored Sep 21, 2021 and Thomas Abraham committed Sep 21, 2021

Add model parameter to enable loading of mcp_ramfw.bin file at the
address 0x0BF80000.
Signed-off-by: Shriram K <shriram.k@arm.com>
Change-Id: If305a95abe4e3e71811b311ec7b2bd6fe26c39f2

Zakaria Zahi authored Sep 16, 2021 and Thomas Abraham committed Sep 16, 2021

Allow UEFI SCT tests to be executed on additional platforms. This allows
executing the UEFI SCT tests as an independent test outside of ACS test
suite. Independent tests allows for selecting the tests to be executed.
Signed-off-by: Zakaria Zahi <zakaria.zahi@arm.com>
Change-Id: Ib004c2c4cfe7844891a453eba37b3806ec41f83f

Pranav-Madhu authored Sep 16, 2021 and Thomas Abraham committed Sep 16, 2021

Enabling PCIe ACS parameters on root ports are causing SMMU test
engines, connected on these root ports, to go to same IOMMU translation
group. This is causing misconfiguration of MSIs in kvmtool for these
devices when trying to boot VMs with PCI-passthrough I/O virtualized
devices. Therefore, adding these parameters is currently defeating the
purpose of having separate devices for VFIO based virtualization
testing.

These parameters are required to support SBSA PCIe exerciser test cases.
At present the support for PCI MSI is not enabled in GIC from UEFI and
hence the exerciser test cases are skipped. These parameters should be
added back after MSI support is enabled.

Change-Id: I1c99d62dbdb7f89629929b89da85214cdccab54b
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>