Commit 30bb79fb authored by Aditya Angadi's avatar Aditya Angadi Committed by Thomas Abraham
Browse files

product/rdn2: add support for variant 1 of rdn2 platform



Add support for RD-N2 Cfg1 platform. It is a variant of RD-N2 platform
with a reduced 3x3 mesh and core count reduced to 8. PLATFORM_VARIANT
value of this platform is 1.
Signed-off-by: Aditya Angadi's avatarAditya Angadi <aditya.angadi@arm.com>
Change-Id: I088e81a6beff94c889607d9676ab28ef5bbdca64
parent 23151486
......@@ -25,6 +25,7 @@ enum clock_pll_idx {
CLOCK_PLL_IDX_CPU5,
CLOCK_PLL_IDX_CPU6,
CLOCK_PLL_IDX_CPU7,
#if (PLATFORM_VARIANT == 0)
CLOCK_PLL_IDX_CPU8,
CLOCK_PLL_IDX_CPU9,
CLOCK_PLL_IDX_CPU10,
......@@ -33,6 +34,7 @@ enum clock_pll_idx {
CLOCK_PLL_IDX_CPU13,
CLOCK_PLL_IDX_CPU14,
CLOCK_PLL_IDX_CPU15,
#endif
CLOCK_PLL_IDX_SYS,
CLOCK_PLL_IDX_DMC,
CLOCK_PLL_IDX_INTERCONNECT,
......@@ -51,6 +53,7 @@ enum clock_pik_idx {
CLOCK_PIK_IDX_CLUS5_CPU0,
CLOCK_PIK_IDX_CLUS6_CPU0,
CLOCK_PIK_IDX_CLUS7_CPU0,
#if (PLATFORM_VARIANT == 0)
CLOCK_PIK_IDX_CLUS8_CPU0,
CLOCK_PIK_IDX_CLUS9_CPU0,
CLOCK_PIK_IDX_CLUS10_CPU0,
......@@ -59,6 +62,7 @@ enum clock_pik_idx {
CLOCK_PIK_IDX_CLUS13_CPU0,
CLOCK_PIK_IDX_CLUS14_CPU0,
CLOCK_PIK_IDX_CLUS15_CPU0,
#endif
CLOCK_PIK_IDX_DMC,
CLOCK_PIK_IDX_INTERCONNECT,
CLOCK_PIK_IDX_SCP,
......@@ -81,6 +85,7 @@ enum clock_css_idx {
CLOCK_CSS_IDX_CPU_GROUP5,
CLOCK_CSS_IDX_CPU_GROUP6,
CLOCK_CSS_IDX_CPU_GROUP7,
#if (PLATFORM_VARIANT == 0)
CLOCK_CSS_IDX_CPU_GROUP8,
CLOCK_CSS_IDX_CPU_GROUP9,
CLOCK_CSS_IDX_CPU_GROUP10,
......@@ -89,6 +94,7 @@ enum clock_css_idx {
CLOCK_CSS_IDX_CPU_GROUP13,
CLOCK_CSS_IDX_CPU_GROUP14,
CLOCK_CSS_IDX_CPU_GROUP15,
#endif
CLOCK_CSS_IDX_COUNT
};
......@@ -104,6 +110,7 @@ enum clock_idx {
CLOCK_IDX_CPU_GROUP5,
CLOCK_IDX_CPU_GROUP6,
CLOCK_IDX_CPU_GROUP7,
#if (PLATFORM_VARIANT == 0)
CLOCK_IDX_CPU_GROUP8,
CLOCK_IDX_CPU_GROUP9,
CLOCK_IDX_CPU_GROUP10,
......@@ -112,6 +119,7 @@ enum clock_idx {
CLOCK_IDX_CPU_GROUP13,
CLOCK_IDX_CPU_GROUP14,
CLOCK_IDX_CPU_GROUP15,
#endif
CLOCK_IDX_INTERCONNECT,
CLOCK_IDX_COUNT
};
......
......@@ -13,7 +13,11 @@
#define PLATFORM_CORE_PER_CLUSTER_MAX 1
#define CORES_PER_CLUSTER 1
#if (PLATFORM_VARIANT == 0)
#define NUMBER_OF_CLUSTERS 16
#else
#define NUMBER_OF_CLUSTERS 8
#endif
static inline unsigned int platform_get_cluster_count(void)
{
......
......@@ -26,6 +26,7 @@
#define SCP_PLL_CPU5 (SCP_PLL_BASE + 0x00000114)
#define SCP_PLL_CPU6 (SCP_PLL_BASE + 0x00000118)
#define SCP_PLL_CPU7 (SCP_PLL_BASE + 0x0000011C)
#if (PLATFORM_VARIANT == 0)
#define SCP_PLL_CPU8 (SCP_PLL_BASE + 0x00000120)
#define SCP_PLL_CPU9 (SCP_PLL_BASE + 0x00000124)
#define SCP_PLL_CPU10 (SCP_PLL_BASE + 0x00000128)
......@@ -34,5 +35,6 @@
#define SCP_PLL_CPU13 (SCP_PLL_BASE + 0x00000134)
#define SCP_PLL_CPU14 (SCP_PLL_BASE + 0x00000138)
#define SCP_PLL_CPU15 (SCP_PLL_BASE + 0x0000013C)
#endif
#endif /* SCP_SOC_MMAP_H */
......@@ -39,6 +39,7 @@ static const struct fwk_element clock_dev_desc_table[] = {
CLOCK_CPU_GROUP(5),
CLOCK_CPU_GROUP(6),
CLOCK_CPU_GROUP(7),
#if (PLATFORM_VARIANT == 0)
CLOCK_CPU_GROUP(8),
CLOCK_CPU_GROUP(9),
CLOCK_CPU_GROUP(10),
......@@ -47,6 +48,7 @@ static const struct fwk_element clock_dev_desc_table[] = {
CLOCK_CPU_GROUP(13),
CLOCK_CPU_GROUP(14),
CLOCK_CPU_GROUP(15),
#endif
[CLOCK_IDX_INTERCONNECT] = {
.name = "Interconnect",
.data = &((struct mod_clock_dev_config) {
......
......@@ -22,6 +22,7 @@
/*
* CMN700 nodes
*/
#if (PLATFORM_VARIANT == 0)
#define MEM_CNTRL0_ID 64
#define MEM_CNTRL1_ID 128
#define MEM_CNTRL2_ID 192
......@@ -35,7 +36,17 @@
#define NODE_ID_HNI0 0
#define NODE_ID_HNP0 324
#define NODE_ID_SBSX 196
#elif (PLATFORM_VARIANT == 1)
#define MEM_CNTRL0_ID 32
#define MEM_CNTRL1_ID 64
#define NODE_ID_HND 68
#define NODE_ID_HNI0 0
#define NODE_ID_HNP0 2
#define NODE_ID_SBSX 66
#endif
#if (PLATFORM_VARIANT == 0)
static const unsigned int snf_table[] = {
MEM_CNTRL0_ID, /* Maps to HN-F logical node 0 */
MEM_CNTRL0_ID, /* Maps to HN-F logical node 1 */
......@@ -70,6 +81,18 @@ static const unsigned int snf_table[] = {
MEM_CNTRL7_ID, /* Maps to HN-F logical node 30 */
MEM_CNTRL7_ID, /* Maps to HN-F logical node 31 */
};
#elif (PLATFORM_VARIANT == 1)
static const unsigned int snf_table[] = {
MEM_CNTRL0_ID, /* Maps to HN-F logical node 0 */
MEM_CNTRL0_ID, /* Maps to HN-F logical node 1 */
MEM_CNTRL0_ID, /* Maps to HN-F logical node 2 */
MEM_CNTRL0_ID, /* Maps to HN-F logical node 3 */
MEM_CNTRL1_ID, /* Maps to HN-F logical node 4 */
MEM_CNTRL1_ID, /* Maps to HN-F logical node 5 */
MEM_CNTRL1_ID, /* Maps to HN-F logical node 6 */
MEM_CNTRL1_ID, /* Maps to HN-F logical node 7 */
};
#endif
static const struct mod_cmn700_mem_region_map mmap[] = {
{
......@@ -207,8 +230,13 @@ static const struct fwk_element cmn700_device_table[] = {
[0] = { .name = "CMN700 Mesh Config",
.data = &((struct mod_cmn700_config){
.base = SCP_CMN700_BASE,
#if (PLATFORM_VARIANT == 0)
.mesh_size_x = 6,
.mesh_size_y = 6,
#elif (PLATFORM_VARIANT == 1)
.mesh_size_x = 3,
.mesh_size_y = 3,
#endif
.hnd_node_id = NODE_ID_HND,
.snf_table = snf_table,
.snf_count = FWK_ARRAY_SIZE(snf_table),
......
......@@ -84,6 +84,7 @@ MEMBER_TABLE_CPU_GROUP(4);
MEMBER_TABLE_CPU_GROUP(5);
MEMBER_TABLE_CPU_GROUP(6);
MEMBER_TABLE_CPU_GROUP(7);
#if (PLATFORM_VARIANT == 0)
MEMBER_TABLE_CPU_GROUP(8);
MEMBER_TABLE_CPU_GROUP(9);
MEMBER_TABLE_CPU_GROUP(10);
......@@ -92,16 +93,19 @@ MEMBER_TABLE_CPU_GROUP(12);
MEMBER_TABLE_CPU_GROUP(13);
MEMBER_TABLE_CPU_GROUP(14);
MEMBER_TABLE_CPU_GROUP(15);
#endif
static const struct fwk_element css_clock_element_table[] = {
CLOCK_CSS_CPU_GROUP(0), CLOCK_CSS_CPU_GROUP(1),
CLOCK_CSS_CPU_GROUP(2), CLOCK_CSS_CPU_GROUP(3),
CLOCK_CSS_CPU_GROUP(4), CLOCK_CSS_CPU_GROUP(5),
CLOCK_CSS_CPU_GROUP(6), CLOCK_CSS_CPU_GROUP(7),
#if (PLATFORM_VARIANT == 0)
CLOCK_CSS_CPU_GROUP(8), CLOCK_CSS_CPU_GROUP(9),
CLOCK_CSS_CPU_GROUP(10), CLOCK_CSS_CPU_GROUP(11),
CLOCK_CSS_CPU_GROUP(12), CLOCK_CSS_CPU_GROUP(13),
CLOCK_CSS_CPU_GROUP(14), CLOCK_CSS_CPU_GROUP(15),
#endif
[CLOCK_CSS_IDX_COUNT] = { 0 }, /* Termination description. */
};
......
......@@ -52,6 +52,7 @@ static const struct mod_dvfs_domain_config cpu4 = DVFS_DOMAIN_CPU_GROUP_IDX(4);
static const struct mod_dvfs_domain_config cpu5 = DVFS_DOMAIN_CPU_GROUP_IDX(5);
static const struct mod_dvfs_domain_config cpu6 = DVFS_DOMAIN_CPU_GROUP_IDX(6);
static const struct mod_dvfs_domain_config cpu7 = DVFS_DOMAIN_CPU_GROUP_IDX(7);
#if (PLATFORM_VARIANT == 0)
static const struct mod_dvfs_domain_config cpu8 = DVFS_DOMAIN_CPU_GROUP_IDX(8);
static const struct mod_dvfs_domain_config cpu9 = DVFS_DOMAIN_CPU_GROUP_IDX(9);
static const struct mod_dvfs_domain_config cpu10 =
......@@ -66,6 +67,7 @@ static const struct mod_dvfs_domain_config cpu14 =
DVFS_DOMAIN_CPU_GROUP_IDX(14);
static const struct mod_dvfs_domain_config cpu15 =
DVFS_DOMAIN_CPU_GROUP_IDX(15);
#endif
static const struct fwk_element element_table[] = {
DVFS_ELEMENT_IDX(0),
......@@ -76,6 +78,7 @@ static const struct fwk_element element_table[] = {
DVFS_ELEMENT_IDX(5),
DVFS_ELEMENT_IDX(6),
DVFS_ELEMENT_IDX(7),
#if (PLATFORM_VARIANT == 0)
DVFS_ELEMENT_IDX(8),
DVFS_ELEMENT_IDX(9),
DVFS_ELEMENT_IDX(10),
......@@ -84,6 +87,7 @@ static const struct fwk_element element_table[] = {
DVFS_ELEMENT_IDX(13),
DVFS_ELEMENT_IDX(14),
DVFS_ELEMENT_IDX(15),
#endif
{ 0 },
};
......
......@@ -17,6 +17,7 @@ enum dvfs_element_idx {
DVFS_ELEMENT_IDX_CPU5,
DVFS_ELEMENT_IDX_CPU6,
DVFS_ELEMENT_IDX_CPU7,
#if (PLATFORM_VARIANT == 0)
DVFS_ELEMENT_IDX_CPU8,
DVFS_ELEMENT_IDX_CPU9,
DVFS_ELEMENT_IDX_CPU10,
......@@ -25,6 +26,7 @@ enum dvfs_element_idx {
DVFS_ELEMENT_IDX_CPU13,
DVFS_ELEMENT_IDX_CPU14,
DVFS_ELEMENT_IDX_CPU15,
#endif
DVFS_ELEMENT_IDX_COUNT
};
......
......@@ -32,6 +32,7 @@ static const struct fwk_element element_table[] = {
MOCK_PSU_ELEMENT_IDX(5),
MOCK_PSU_ELEMENT_IDX(6),
MOCK_PSU_ELEMENT_IDX(7),
#if (PLATFORM_VARIANT == 0)
MOCK_PSU_ELEMENT_IDX(8),
MOCK_PSU_ELEMENT_IDX(9),
MOCK_PSU_ELEMENT_IDX(10),
......@@ -40,6 +41,7 @@ static const struct fwk_element element_table[] = {
MOCK_PSU_ELEMENT_IDX(13),
MOCK_PSU_ELEMENT_IDX(14),
MOCK_PSU_ELEMENT_IDX(15),
#endif
{ 0 },
};
......
......@@ -117,6 +117,7 @@ static const struct fwk_element pik_clock_element_table[] = {
CLOCK_PLL_CLUSn_CPU(5),
CLOCK_PLL_CLUSn_CPU(6),
CLOCK_PLL_CLUSn_CPU(7),
#if (PLATFORM_VARIANT == 0)
CLOCK_PLL_CLUSn_CPU(8),
CLOCK_PLL_CLUSn_CPU(9),
CLOCK_PLL_CLUSn_CPU(10),
......@@ -125,6 +126,7 @@ static const struct fwk_element pik_clock_element_table[] = {
CLOCK_PLL_CLUSn_CPU(13),
CLOCK_PLL_CLUSn_CPU(14),
CLOCK_PLL_CLUSn_CPU(15),
#endif
[CLOCK_PIK_IDX_DMC] = {
.name = "DMC",
.data = &((struct mod_pik_clock_dev_config) {
......
......@@ -29,6 +29,7 @@ static const struct fwk_element element_table[] = {
PSU_ELEMENT_IDX(5),
PSU_ELEMENT_IDX(6),
PSU_ELEMENT_IDX(7),
#if (PLATFORM_VARIANT == 0)
PSU_ELEMENT_IDX(8),
PSU_ELEMENT_IDX(9),
PSU_ELEMENT_IDX(10),
......@@ -37,6 +38,7 @@ static const struct fwk_element element_table[] = {
PSU_ELEMENT_IDX(13),
PSU_ELEMENT_IDX(14),
PSU_ELEMENT_IDX(15),
#endif
{ 0 },
};
......
......@@ -71,6 +71,7 @@ static const struct mod_scmi_perf_domain_config domains[] = {
.fast_channels_addr_ap = (uint64_t[])FAST_CHANNEL_ADDRESS_AP(6) },
[7] = { .fast_channels_addr_scp = (uint64_t[])FAST_CHANNEL_ADDRESS_SCP(7),
.fast_channels_addr_ap = (uint64_t[])FAST_CHANNEL_ADDRESS_AP(7) },
#if (PLATFORM_VARIANT == 0)
[8] = { .fast_channels_addr_scp = (uint64_t[])FAST_CHANNEL_ADDRESS_SCP(8),
.fast_channels_addr_ap = (uint64_t[])FAST_CHANNEL_ADDRESS_AP(8) },
[9] = { .fast_channels_addr_scp = (uint64_t[])FAST_CHANNEL_ADDRESS_SCP(9),
......@@ -87,9 +88,14 @@ static const struct mod_scmi_perf_domain_config domains[] = {
.fast_channels_addr_ap = (uint64_t[])FAST_CHANNEL_ADDRESS_AP(14) },
[15] = { .fast_channels_addr_scp = (uint64_t[])FAST_CHANNEL_ADDRESS_SCP(15),
.fast_channels_addr_ap = (uint64_t[])FAST_CHANNEL_ADDRESS_AP(15) },
#endif
};
#else
#if (PLATFORM_VARIANT == 0)
static const struct mod_scmi_perf_domain_config domains[16] = { 0 };
#else
static const struct mod_scmi_perf_domain_config domains[8] = { 0 };
#endif
#endif
const struct fwk_module_config config_scmi_perf = {
......
......@@ -39,6 +39,7 @@ static const struct fwk_element system_pll_element_table[] = {
CLOCK_PLL_IDX_CPU(5),
CLOCK_PLL_IDX_CPU(6),
CLOCK_PLL_IDX_CPU(7),
#if (PLATFORM_VARIANT == 0)
CLOCK_PLL_IDX_CPU(8),
CLOCK_PLL_IDX_CPU(9),
CLOCK_PLL_IDX_CPU(10),
......@@ -47,6 +48,7 @@ static const struct fwk_element system_pll_element_table[] = {
CLOCK_PLL_IDX_CPU(13),
CLOCK_PLL_IDX_CPU(14),
CLOCK_PLL_IDX_CPU(15),
#endif
[CLOCK_PLL_IDX_SYS] = {
.name = "SYS_PLL",
.data = &((struct mod_system_pll_dev_config) {
......
......@@ -17,7 +17,11 @@ static const struct fwk_element subsystem_table[] = {
{ .name = "RD-N2",
.data =
&(struct mod_sid_subsystem_config){
#if (PLATFORM_VARIANT == 0)
.part_number = 0x7B7,
#else
.part_number = 0x7B6,
#endif
} },
{ 0 },
};
......
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