Commit 6c2ff324 authored by Vijayenthiran Subramaniam's avatar Vijayenthiran Subramaniam Committed by Thomas Abraham
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product/rdn2: add config data for pcie integ control module



Add configuration data for the PCIe control module. Root Complex x16 of
IO macro 0-4 (IO Macro 0-1 in case of platform variant 1) are enabled
and the address used are matched with the ECAM and MMIO addresses used
in the CMN-700 configuration data.
Signed-off-by: Vijayenthiran Subramaniam's avatarVijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I5113abe28e261605b8f09888c21d102ce95481f0
parent 3623c385
......@@ -40,4 +40,17 @@
#define SCP_MHU_SCP_AP_SND_S_CLUS0 (0x45020000)
#define SCP_MHU_SCP_AP_RCV_S_CLUS0 (0x45030000)
/*
* Macro to convert the AP address to SCP address to access through System
* Access Port 0
*/
#define SCP_SYSTEM_ACCESS_PORT0_ADDR(addr) (addr + 0x20000000)
/* PCIe Related memory map */
#define PCIE_INTEG_CTRL_REG_BASE0 (SCP_SYSTEM_ACCESS_PORT0_ADDR(0x40D00000))
#define PCIE_INTEG_CTRL_REG_BASE1 (SCP_SYSTEM_ACCESS_PORT0_ADDR(0x42D00000))
#define PCIE_INTEG_CTRL_REG_BASE2 (SCP_SYSTEM_ACCESS_PORT0_ADDR(0x44D00000))
#define PCIE_INTEG_CTRL_REG_BASE3 (SCP_SYSTEM_ACCESS_PORT0_ADDR(0x46D00000))
#define PCIE_INTEG_CTRL_REG_BASE4 (SCP_SYSTEM_ACCESS_PORT0_ADDR(0x48D00000))
#endif /* SCP_CSS_MMAP_H */
......@@ -63,4 +63,14 @@
#define SCP_SCMI_FAST_CHANNEL_BASE \
(SCP_SDS_NONSECURE_BASE + SCP_SDS_NONSECURE_SIZE)
/* PCIe ECAM and MMIO addresses */
#define AP_ECAM_BASE (0x1010000000ULL)
#define AP_ECAM_SIZE_PER_RC (32ULL * FWK_MIB)
#define AP_MMIOL_BASE (0x60000000)
#define AP_MMIOL_SIZE_PER_RC (64 * FWK_MIB)
#define AP_MMIOH_BASE (0x4000000000ULL)
#define AP_MMIOH_SIZE_PER_RC (32ULL * FWK_GIB)
#endif /* SCP_SOFTWARE_MMAP_H */
......@@ -6,6 +6,8 @@
*/
#include "clock_soc.h"
#include "scp_css_mmap.h"
#include "scp_software_mmap.h"
#include <mod_pcie_integ_ctrl.h>
......@@ -13,18 +15,86 @@
#include <fwk_module.h>
#include <fwk_module_idx.h>
#define START_ADDR(index, base, size) (base + (size * index))
#define END_ADDR(index, base, size) (base + (size * (index + 1ULL)) - 1ULL)
static const struct io_macro_instance io_macro_mmap_table[] = {
{
/* IO Macro 0 */
.reg_base = PCIE_INTEG_CTRL_REG_BASE0,
.x16_ecam_mmio_mmap = {
.valid = true,
.ecam1_start_addr = START_ADDR(0, AP_ECAM_BASE, AP_ECAM_SIZE_PER_RC),
.ecam1_end_addr = END_ADDR(0, AP_ECAM_BASE, AP_ECAM_SIZE_PER_RC),
.mmiol_start_addr = START_ADDR (0, AP_MMIOL_BASE, AP_MMIOL_SIZE_PER_RC),
.mmiol_end_addr = END_ADDR(0, AP_MMIOL_BASE, AP_MMIOL_SIZE_PER_RC),
.mmioh_start_addr = START_ADDR(0, AP_MMIOH_BASE, AP_MMIOH_SIZE_PER_RC),
.mmioh_end_addr = END_ADDR(0, AP_MMIOH_BASE, AP_MMIOH_SIZE_PER_RC),
},
},
{
/* IO Macro 1 */
.reg_base = PCIE_INTEG_CTRL_REG_BASE1,
.x16_ecam_mmio_mmap = {
.valid = true,
.ecam1_start_addr = START_ADDR(1, AP_ECAM_BASE, AP_ECAM_SIZE_PER_RC),
.ecam1_end_addr = END_ADDR(1, AP_ECAM_BASE, AP_ECAM_SIZE_PER_RC),
.mmiol_start_addr = START_ADDR (1, AP_MMIOL_BASE, AP_MMIOL_SIZE_PER_RC),
.mmiol_end_addr = END_ADDR(1, AP_MMIOL_BASE, AP_MMIOL_SIZE_PER_RC),
.mmioh_start_addr = START_ADDR(1, AP_MMIOH_BASE, AP_MMIOH_SIZE_PER_RC),
.mmioh_end_addr = END_ADDR(1, AP_MMIOH_BASE, AP_MMIOH_SIZE_PER_RC),
},
},
#if (PLATFORM_VARIANT == 0)
{
/* IO Macro 2 */
.reg_base = PCIE_INTEG_CTRL_REG_BASE2,
.x16_ecam_mmio_mmap = {
.valid = true,
.ecam1_start_addr = START_ADDR(2, AP_ECAM_BASE, AP_ECAM_SIZE_PER_RC),
.ecam1_end_addr = END_ADDR(2, AP_ECAM_BASE, AP_ECAM_SIZE_PER_RC),
.mmiol_start_addr = START_ADDR (2, AP_MMIOL_BASE, AP_MMIOL_SIZE_PER_RC),
.mmiol_end_addr = END_ADDR(2, AP_MMIOL_BASE, AP_MMIOL_SIZE_PER_RC),
.mmioh_start_addr = START_ADDR(2, AP_MMIOH_BASE, AP_MMIOH_SIZE_PER_RC),
.mmioh_end_addr = END_ADDR(2, AP_MMIOH_BASE, AP_MMIOH_SIZE_PER_RC),
},
},
{
/* IO Macro 3 */
.reg_base = PCIE_INTEG_CTRL_REG_BASE3,
.x16_ecam_mmio_mmap = {
.valid = true,
.ecam1_start_addr = START_ADDR(3, AP_ECAM_BASE, AP_ECAM_SIZE_PER_RC),
.ecam1_end_addr = END_ADDR(3, AP_ECAM_BASE, AP_ECAM_SIZE_PER_RC),
.mmiol_start_addr = START_ADDR (3, AP_MMIOL_BASE, AP_MMIOL_SIZE_PER_RC),
.mmiol_end_addr = END_ADDR(3, AP_MMIOL_BASE, AP_MMIOL_SIZE_PER_RC),
.mmioh_start_addr = START_ADDR(3, AP_MMIOH_BASE, AP_MMIOH_SIZE_PER_RC),
.mmioh_end_addr = END_ADDR(3, AP_MMIOH_BASE, AP_MMIOH_SIZE_PER_RC),
},
},
{
/* IO Macro 4 */
.reg_base = PCIE_INTEG_CTRL_REG_BASE4,
.x16_ecam_mmio_mmap = {
.valid = true,
.ecam1_start_addr = START_ADDR(4, AP_ECAM_BASE, AP_ECAM_SIZE_PER_RC),
.ecam1_end_addr = END_ADDR(4, AP_ECAM_BASE, AP_ECAM_SIZE_PER_RC),
.mmiol_start_addr = START_ADDR (4, AP_MMIOL_BASE, AP_MMIOL_SIZE_PER_RC),
.mmiol_end_addr = END_ADDR(4, AP_MMIOL_BASE, AP_MMIOL_SIZE_PER_RC),
.mmioh_start_addr = START_ADDR(4, AP_MMIOH_BASE, AP_MMIOH_SIZE_PER_RC),
.mmioh_end_addr = END_ADDR(4, AP_MMIOH_BASE, AP_MMIOH_SIZE_PER_RC),
},
},
#endif
};
/*
* PCIe integration control module configuration
*/
static const struct mod_pcie_integ_ctrl_config pcie_integ_ctrl_data = {
.reg_base = 0x60D00000,
.ecam_mmio_mmap = {
.ecam1_start_addr = 0x60000000,
.ecam1_end_addr = 0x7FFFFFFF,
.mmiol_start_addr = 0x1010000000,
.mmiol_end_addr = 0x104FFFFFFF,
},
.io_macro_count = FWK_ARRAY_SIZE(io_macro_mmap_table),
.io_macro_mmap_table = io_macro_mmap_table,
.clock_id =
FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_INTERCONNECT),
};
......
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