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Commit 0b18d5a5 authored by Madhukar Pappireddy's avatar Madhukar Pappireddy Committed by TrustedFirmware Code Review
Browse files

Merge changes from topic "zynqmp-misc-enhancement" into integration

* changes:
  plat: xilinx: zynqmp: Enable log messages for debug
  plat: zynqmp: Change macro name of PM_BOOT_HEALTH_STATUS_REG
parents cd6eaab6 490d81d2
......@@ -104,9 +104,12 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
else if (ret != FSBL_HANDOFF_SUCCESS)
panic();
}
NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
if (bl32_image_ep_info.pc) {
VERBOSE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
}
if (bl33_image_ep_info.pc) {
VERBOSE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
}
}
/* Enable the test setup */
......
/*
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -341,8 +341,9 @@
#define PGGS_BASEADDR (0xFFD80050U)
#define PGGS_NUM_REGS U(4)
/* Warm restart boot health status register and mask */
#define PM_BOOT_HEALTH_STATUS_REG (GGS_BASEADDR + U(0x10))
/* PMU GGS4 register 4 is used for warm restart boot health status */
#define PMU_GLOBAL_GEN_STORAGE4 (GGS_BASEADDR + 0x10)
/* Warm restart boot health status mask */
#define PM_BOOT_HEALTH_STATUS_MASK U(0x01)
/*AFI registers */
......
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -575,7 +575,7 @@ static enum pm_ret_status pm_ioctl_ulpi_reset(void)
*/
static enum pm_ret_status pm_ioctl_set_boot_health_status(unsigned int value)
{
return pm_mmio_write(PM_BOOT_HEALTH_STATUS_REG,
return pm_mmio_write(PMU_GLOBAL_GEN_STORAGE4,
PM_BOOT_HEALTH_STATUS_MASK, value);
}
......
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