Commit 1a3f02b5 authored by Rajan Vaja's avatar Rajan Vaja Committed by Jolly Shah
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zynqmp: pm: Implement clock APIs



- Add clock entries and information to clock database.
- Implement APIs to provide clock topology and other
  information to caller.
- Implement APIs to control clocks and PLLs.

Signed-off-by: default avatarRajan Vaja <rajanv@xilinx.com>
Signed-off-by: default avatarJolly Shah <jollys@xilinx.com>
parent caae497d
......@@ -11,9 +11,264 @@
#ifndef _PM_API_CLOCK_H_
#define _PM_API_CLOCK_H_
#include <utils_def.h>
#include "pm_common.h"
#define CLK_NAME_LEN 15
#define MAX_PARENTS 100
#define CLK_NA_PARENT -1
#define CLK_DUMMY_PARENT -2
/* Flags for parent id */
#define PARENT_CLK_SELF 0
#define PARENT_CLK_NODE1 1
#define PARENT_CLK_NODE2 2
#define PARENT_CLK_NODE3 3
#define PARENT_CLK_NODE4 4
#define PARENT_CLK_EXTERNAL 5
#define PARENT_CLK_MIO0_MIO77 6
#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
/* unused */
#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
/* parents need enable during gate/ungate, set rate and re-parent */
#define CLK_OPS_PARENT_ENABLE BIT(12)
#define CLK_FRAC BIT(13)
#define CLK_DIVIDER_ONE_BASED BIT(0)
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
#define CLK_DIVIDER_HIWORD_MASK BIT(3)
#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
#define CLK_DIVIDER_READ_ONLY BIT(5)
#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
#define END_OF_CLK "END_OF_CLK"
enum clock_ids {
CLK_IOPLL,
CLK_RPLL,
CLK_APLL,
CLK_DPLL,
CLK_VPLL,
CLK_IOPLL_TO_FPD,
CLK_RPLL_TO_FPD,
CLK_APLL_TO_LPD,
CLK_DPLL_TO_LPD,
CLK_VPLL_TO_LPD,
CLK_ACPU,
CLK_ACPU_HALF,
CLK_DBG_FPD,
CLK_DBG_LPD,
CLK_DBG_TRACE,
CLK_DBG_TSTMP,
CLK_DP_VIDEO_REF,
CLK_DP_AUDIO_REF,
CLK_DP_STC_REF,
CLK_GDMA_REF,
CLK_DPDMA_REF,
CLK_DDR_REF,
CLK_SATA_REF,
CLK_PCIE_REF,
CLK_GPU_REF,
CLK_GPU_PP0_REF,
CLK_GPU_PP1_REF,
CLK_TOPSW_MAIN,
CLK_TOPSW_LSBUS,
CLK_GTGREF0_REF,
CLK_LPD_SWITCH,
CLK_LPD_LSBUS,
CLK_USB0_BUS_REF,
CLK_USB1_BUS_REF,
CLK_USB3_DUAL_REF,
CLK_USB0,
CLK_USB1,
CLK_CPU_R5,
CLK_CPU_R5_CORE,
CLK_CSU_SPB,
CLK_CSU_PLL,
CLK_PCAP,
CLK_IOU_SWITCH,
CLK_GEM_TSU_REF,
CLK_GEM_TSU,
CLK_GEM0_REF,
CLK_GEM1_REF,
CLK_GEM2_REF,
CLK_GEM3_REF,
CLK_GEM0_TX,
CLK_GEM1_TX,
CLK_GEM2_TX,
CLK_GEM3_TX,
CLK_QSPI_REF,
CLK_SDIO0_REF,
CLK_SDIO1_REF,
CLK_UART0_REF,
CLK_UART1_REF,
CLK_SPI0_REF,
CLK_SPI1_REF,
CLK_NAND_REF,
CLK_I2C0_REF,
CLK_I2C1_REF,
CLK_CAN0_REF,
CLK_CAN1_REF,
CLK_CAN0,
CLK_CAN1,
CLK_DLL_REF,
CLK_ADMA_REF,
CLK_TIMESTAMP_REF,
CLK_AMS_REF,
CLK_PL0_REF,
CLK_PL1_REF,
CLK_PL2_REF,
CLK_PL3_REF,
CLK_WDT,
CLK_IOPLL_INT,
CLK_IOPLL_PRE_SRC,
CLK_IOPLL_HALF,
CLK_IOPLL_INT_MUX,
CLK_IOPLL_POST_SRC,
CLK_RPLL_INT,
CLK_RPLL_PRE_SRC,
CLK_RPLL_HALF,
CLK_RPLL_INT_MUX,
CLK_RPLL_POST_SRC,
CLK_APLL_INT,
CLK_APLL_PRE_SRC,
CLK_APLL_HALF,
CLK_APLL_INT_MUX,
CLK_APLL_POST_SRC,
CLK_DPLL_INT,
CLK_DPLL_PRE_SRC,
CLK_DPLL_HALF,
CLK_DPLL_INT_MUX,
CLK_DPLL_POST_SRC,
CLK_VPLL_INT,
CLK_VPLL_PRE_SRC,
CLK_VPLL_HALF,
CLK_VPLL_INT_MUX,
CLK_VPLL_POST_SRC,
CLK_CAN0_MIO,
CLK_CAN1_MIO,
CLK_MAX_OUTPUT_CLK,
};
enum external_clk_ids {
EXT_CLK_PSS_REF = CLK_MAX_OUTPUT_CLK,
EXT_CLK_VIDEO,
EXT_CLK_PSS_ALT_REF,
EXT_CLK_AUX_REF,
EXT_CLK_GT_CRX_REF,
EXT_CLK_SWDT0,
EXT_CLK_SWDT1,
EXT_CLK_GEM0_EMIO,
EXT_CLK_GEM1_EMIO,
EXT_CLK_GEM2_EMIO,
EXT_CLK_GEM3_EMIO,
EXT_CLK_MIO50_OR_MIO51,
EXT_CLK_MIO0,
EXT_CLK_MIO1,
EXT_CLK_MIO2,
EXT_CLK_MIO3,
EXT_CLK_MIO4,
EXT_CLK_MIO5,
EXT_CLK_MIO6,
EXT_CLK_MIO7,
EXT_CLK_MIO8,
EXT_CLK_MIO9,
EXT_CLK_MIO10,
EXT_CLK_MIO11,
EXT_CLK_MIO12,
EXT_CLK_MIO13,
EXT_CLK_MIO14,
EXT_CLK_MIO15,
EXT_CLK_MIO16,
EXT_CLK_MIO17,
EXT_CLK_MIO18,
EXT_CLK_MIO19,
EXT_CLK_MIO20,
EXT_CLK_MIO21,
EXT_CLK_MIO22,
EXT_CLK_MIO23,
EXT_CLK_MIO24,
EXT_CLK_MIO25,
EXT_CLK_MIO26,
EXT_CLK_MIO27,
EXT_CLK_MIO28,
EXT_CLK_MIO29,
EXT_CLK_MIO30,
EXT_CLK_MIO31,
EXT_CLK_MIO32,
EXT_CLK_MIO33,
EXT_CLK_MIO34,
EXT_CLK_MIO35,
EXT_CLK_MIO36,
EXT_CLK_MIO37,
EXT_CLK_MIO38,
EXT_CLK_MIO39,
EXT_CLK_MIO40,
EXT_CLK_MIO41,
EXT_CLK_MIO42,
EXT_CLK_MIO43,
EXT_CLK_MIO44,
EXT_CLK_MIO45,
EXT_CLK_MIO46,
EXT_CLK_MIO47,
EXT_CLK_MIO48,
EXT_CLK_MIO49,
EXT_CLK_MIO50,
EXT_CLK_MIO51,
EXT_CLK_MIO52,
EXT_CLK_MIO53,
EXT_CLK_MIO54,
EXT_CLK_MIO55,
EXT_CLK_MIO56,
EXT_CLK_MIO57,
EXT_CLK_MIO58,
EXT_CLK_MIO59,
EXT_CLK_MIO60,
EXT_CLK_MIO61,
EXT_CLK_MIO62,
EXT_CLK_MIO63,
EXT_CLK_MIO64,
EXT_CLK_MIO65,
EXT_CLK_MIO66,
EXT_CLK_MIO67,
EXT_CLK_MIO68,
EXT_CLK_MIO69,
EXT_CLK_MIO70,
EXT_CLK_MIO71,
EXT_CLK_MIO72,
EXT_CLK_MIO73,
EXT_CLK_MIO74,
EXT_CLK_MIO75,
EXT_CLK_MIO76,
EXT_CLK_MIO77,
CLK_MAX,
};
enum clk_type {
CLK_TYPE_OUTPUT,
CLK_TYPE_EXTERNAL,
};
enum topology_type {
TYPE_INVALID,
TYPE_MUX,
TYPE_PLL,
TYPE_FIXEDFACTOR,
TYPE_DIV1,
TYPE_DIV2,
TYPE_GATE,
};
enum pm_ret_status pm_api_clock_get_name(unsigned int clock_id, char *name);
enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id,
......@@ -51,4 +306,5 @@ enum pm_ret_status pm_api_clk_set_pll_frac_data(unsigned int pll,
unsigned int data);
enum pm_ret_status pm_api_clk_get_pll_frac_data(unsigned int pll,
unsigned int *data);
#endif /* _PM_API_CLOCK_H_ */
......@@ -35,6 +35,7 @@
/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
#define CRF_APB_BASE 0xFD1A0000
#define CRF_APB_SIZE 0x00600000
#define CRF_APB_CLK_BASE 0xFD1A0020
/* CRF registers and bitfields */
#define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104)
......@@ -44,10 +45,10 @@
/* CRL registers and bitfields */
#define CRL_APB_BASE 0xFF5E0000
#define CRL_APB_RPLL_CTRL (CRL_APB_BASE + 0x30)
#define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200)
#define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218)
#define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C)
#define CRL_APB_CLK_BASE 0xFF5E0020
#define CRL_APB_RPU_AMBA_RESET (1 << 2)
#define CRL_APB_RPLL_CTRL_BYPASS (1 << 3)
......@@ -225,4 +226,81 @@
#define ZYNQMP_SD_OTAPDLYENA_MASK 0x40
#define ZYNQMP_SD_OTAPDLYENA 0x40
/* Clock control registers */
/* Full power domain clocks */
#define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00)
#define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c)
#define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18)
#define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24)
#define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28)
#define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c)
#define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30)
/* Peripheral clocks */
#define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40)
#define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44)
#define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48)
#define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50)
#define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54)
#define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c)
#define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60)
#define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64)
#define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80)
#define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94)
#define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98)
#define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c)
#define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0)
#define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4)
#define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8)
#define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8)
/* Low power domain clocks */
#define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00)
#define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10)
#define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20)
#define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24)
#define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28)
/* Peripheral clocks */
#define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c)
#define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30)
#define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34)
#define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38)
#define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c)
#define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40)
#define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44)
#define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48)
#define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c)
#define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50)
#define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54)
#define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58)
#define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c)
#define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60)
#define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64)
#define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68)
#define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70)
#define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c)
#define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80)
#define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84)
#define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88)
#define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c)
#define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90)
#define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94)
#define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98)
#define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0)
#define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4)
#define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8)
#define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac)
#define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4)
#define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc)
#define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4)
#define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc)
#define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0)
#define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4)
#define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8)
#define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100)
#define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104)
#define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108)
#define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308)
#define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304)
#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300)
#endif /* __ZYNQMP_DEF_H__ */
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