Commit 1e66bacb authored by Konstantin Porotchkin's avatar Konstantin Porotchkin
Browse files

plat: marvell: Add support for Armada-37xx SoC platform



Add supprot for Marvell platforms based on Armada-37xx SoC.
This includes support for the official Armada-3720 modular
development board and EspressoBin community board.
The Armada-37xx SoC contains dual Cortex-A53 Application CPU,
single secure CPU (Cortex-M3) and the following interfaces:
- SATA 3.0
- USB 3.0 and USB 2.0
- PCIe
- SDIO (supports boot from eMMC)
- SPI
- UART
- I2c
- Gigabit Ethernet

Signed-off-by: default avatarKonstantin Porotchkin <kostap@marvell.com>
parent 19112b79
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef __ARMADA_COMMON_H__
#define __ARMADA_COMMON_H__
#include <io_addr_dec.h>
#include <stdint.h>
int marvell_get_io_dec_win_conf(struct dec_win_config **win, uint32_t *size);
#endif /* __ARMADA_COMMON_H__ */
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef __BOARD_MARVELL_DEF_H__
#define __BOARD_MARVELL_DEF_H__
/*
* Required platform porting definitions common to all ARM
* development platforms
*/
/* Size of cacheable stacks */
#if IMAGE_BL1
#if TRUSTED_BOARD_BOOT
# define PLATFORM_STACK_SIZE 0x1000
#else
# define PLATFORM_STACK_SIZE 0x440
#endif
#elif IMAGE_BL2
# if TRUSTED_BOARD_BOOT
# define PLATFORM_STACK_SIZE 0x1000
# else
# define PLATFORM_STACK_SIZE 0x400
# endif
#elif IMAGE_BL31
# define PLATFORM_STACK_SIZE 0x400
#elif IMAGE_BL32
# define PLATFORM_STACK_SIZE 0x440
#endif
/*
* PLAT_MARVELL_MMAP_ENTRIES depends on the number of entries in the
* plat_arm_mmap array defined for each BL stage.
*/
#if IMAGE_BLE
# define PLAT_MARVELL_MMAP_ENTRIES 3
#endif
#if IMAGE_BL1
# if TRUSTED_BOARD_BOOT
# define PLAT_MARVELL_MMAP_ENTRIES 7
# else
# define PLAT_MARVELL_MMAP_ENTRIES 6
# endif /* TRUSTED_BOARD_BOOT */
#endif
#if IMAGE_BL2
# define PLAT_MARVELL_MMAP_ENTRIES 8
#endif
#if IMAGE_BL31
#define PLAT_MARVELL_MMAP_ENTRIES 5
#endif
/*
* Platform specific page table and MMU setup constants
*/
#if IMAGE_BL1
#define MAX_XLAT_TABLES 4
#elif IMAGE_BLE
# define MAX_XLAT_TABLES 4
#elif IMAGE_BL2
# define MAX_XLAT_TABLES 4
#elif IMAGE_BL31
# define MAX_XLAT_TABLES 4
#elif IMAGE_BL32
# define MAX_XLAT_TABLES 4
#endif
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
#define PLAT_MARVELL_TRUSTED_SRAM_SIZE 0x80000 /* 512 KB */
#endif /* __BOARD_MARVELL_DEF_H__ */
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef __MARVELL_DEF_H__
#define __MARVELL_DEF_H__
#include <arch.h>
#include <common_def.h>
#include <platform_def.h>
#include <tbbr_img_def.h>
#include <xlat_tables.h>
/****************************************************************************
* Definitions common to all MARVELL standard platforms
****************************************************************************
*/
/* Special value used to verify platform parameters from BL2 to BL31 */
#define MARVELL_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
#define PLAT_MARVELL_NORTHB_COUNT 1
#define PLAT_MARVELL_CLUSTER_COUNT 1
#define MARVELL_CACHE_WRITEBACK_SHIFT 6
/*
* Macros mapping the MPIDR Affinity levels to MARVELL Platform Power levels.
* The power levels have a 1:1 mapping with the MPIDR affinity levels.
*/
#define MARVELL_PWR_LVL0 MPIDR_AFFLVL0
#define MARVELL_PWR_LVL1 MPIDR_AFFLVL1
#define MARVELL_PWR_LVL2 MPIDR_AFFLVL2
/*
* Macros for local power states in Marvell platforms encoded by State-ID field
* within the power-state parameter.
*/
/* Local power state for power domains in Run state. */
#define MARVELL_LOCAL_STATE_RUN 0
/* Local power state for retention. Valid only for CPU power domains */
#define MARVELL_LOCAL_STATE_RET 1
/* Local power state for OFF/power-down.
* Valid for CPU and cluster power domains
*/
#define MARVELL_LOCAL_STATE_OFF 2
/* The first 4KB of Trusted SRAM are used as shared memory */
#define MARVELL_TRUSTED_SRAM_BASE PLAT_MARVELL_ATF_BASE
#define MARVELL_SHARED_RAM_BASE MARVELL_TRUSTED_SRAM_BASE
#define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
/* The remaining Trusted SRAM is used to load the BL images */
#define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \
MARVELL_SHARED_RAM_SIZE)
#define MARVELL_BL_RAM_SIZE (PLAT_MARVELL_TRUSTED_SRAM_SIZE - \
MARVELL_SHARED_RAM_SIZE)
#define MARVELL_DRAM_BASE ULL(0x0)
#define MARVELL_DRAM_SIZE ULL(0x20000000)
#define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \
MARVELL_DRAM_SIZE - 1)
#define MARVELL_IRQ_SEC_PHY_TIMER 29
#define MARVELL_IRQ_SEC_SGI_0 8
#define MARVELL_IRQ_SEC_SGI_1 9
#define MARVELL_IRQ_SEC_SGI_2 10
#define MARVELL_IRQ_SEC_SGI_3 11
#define MARVELL_IRQ_SEC_SGI_4 12
#define MARVELL_IRQ_SEC_SGI_5 13
#define MARVELL_IRQ_SEC_SGI_6 14
#define MARVELL_IRQ_SEC_SGI_7 15
#define MARVELL_MAP_SHARED_RAM MAP_REGION_FLAT( \
MARVELL_SHARED_RAM_BASE, \
MARVELL_SHARED_RAM_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
#define MARVELL_MAP_DRAM MAP_REGION_FLAT( \
MARVELL_DRAM_BASE, \
MARVELL_DRAM_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
/*
* The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
#if USE_COHERENT_MEM
#define MARVELL_BL_REGIONS 3
#else
#define MARVELL_BL_REGIONS 2
#endif
#define MAX_MMAP_REGIONS (PLAT_MARVELL_MMAP_ENTRIES + \
MARVELL_BL_REGIONS)
#define MARVELL_CONSOLE_BAUDRATE 115200
/****************************************************************************
* Required platform porting definitions common to all MARVELL std. platforms
****************************************************************************
*/
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
/*
* This macro defines the deepest retention state possible. A higher state
* id will represent an invalid or a power down state.
*/
#define PLAT_MAX_RET_STATE MARVELL_LOCAL_STATE_RET
/*
* This macro defines the deepest power down states possible. Any state ID
* higher than this is invalid.
*/
#define PLAT_MAX_OFF_STATE MARVELL_LOCAL_STATE_OFF
#define PLATFORM_CORE_COUNT PLAT_MARVELL_CLUSTER_CORE_COUNT
/*
* Some data must be aligned on the biggest cache line size in the platform.
* This is known only to the platform as it might have a combination of
* integrated and external caches.
*/
#define CACHE_WRITEBACK_GRANULE (1 << MARVELL_CACHE_WRITEBACK_SHIFT)
/*****************************************************************************
* BL1 specific defines.
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
* addresses.
*****************************************************************************
*/
#define BL1_RO_BASE PLAT_MARVELL_TRUSTED_ROM_BASE
#define BL1_RO_LIMIT (PLAT_MARVELL_TRUSTED_ROM_BASE \
+ PLAT_MARVELL_TRUSTED_ROM_SIZE)
/*
* Put BL1 RW at the top of the Trusted SRAM.
*/
#define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \
MARVELL_BL_RAM_SIZE - \
PLAT_MARVELL_MAX_BL1_RW_SIZE)
#define BL1_RW_LIMIT (MARVELL_BL_RAM_BASE + MARVELL_BL_RAM_SIZE)
/*****************************************************************************
* BL2 specific defines.
*****************************************************************************
*/
/*
* Put BL2 just below BL31.
*/
#define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE)
#define BL2_LIMIT BL31_BASE
/*****************************************************************************
* BL31 specific defines.
*****************************************************************************
*/
/*
* Put BL31 at the top of the Trusted SRAM.
*/
#define BL31_BASE (MARVELL_BL_RAM_BASE + \
MARVELL_BL_RAM_SIZE - \
PLAT_MARVEL_MAX_BL31_SIZE)
#define BL31_PROGBITS_LIMIT BL1_RW_BASE
#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \
MARVELL_BL_RAM_SIZE)
#endif /* __MARVELL_DEF_H__ */
/*
* Copyright (C) 2016 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef __PLAT_MARVELL_H__
#define __PLAT_MARVELL_H__
#include <bl_common.h>
#include <cassert.h>
#include <cpu_data.h>
#include <stdint.h>
#include <xlat_tables.h>
/*
* Extern declarations common to Marvell standard platforms
*/
extern const mmap_region_t plat_marvell_mmap[];
#define MARVELL_CASSERT_MMAP \
CASSERT((ARRAY_SIZE(plat_marvell_mmap) + MARVELL_BL_REGIONS) \
<= MAX_MMAP_REGIONS, \
assert_max_mmap_regions)
/*
* Utility functions common to Marvell standard platforms
*/
void marvell_setup_page_tables(uintptr_t total_base,
size_t total_size,
uintptr_t code_start,
uintptr_t code_limit,
uintptr_t rodata_start,
uintptr_t rodata_limit
#if USE_COHERENT_MEM
, uintptr_t coh_start,
uintptr_t coh_limit
#endif
);
/* IO storage utility functions */
void marvell_io_setup(void);
/* Systimer utility function */
void marvell_configure_sys_timer(void);
/* Topology utility function */
int marvell_check_mpidr(u_register_t mpidr);
/* BL1 utility functions */
void marvell_bl1_early_platform_setup(void);
void marvell_bl1_platform_setup(void);
void marvell_bl1_plat_arch_setup(void);
/* BL2 utility functions */
void marvell_bl2_early_platform_setup(meminfo_t *mem_layout);
void marvell_bl2_platform_setup(void);
void marvell_bl2_plat_arch_setup(void);
uint32_t marvell_get_spsr_for_bl32_entry(void);
uint32_t marvell_get_spsr_for_bl33_entry(void);
/* BL31 utility functions */
void marvell_bl31_early_platform_setup(void *from_bl2,
uintptr_t soc_fw_config,
uintptr_t hw_config,
void *plat_params_from_bl2);
void marvell_bl31_platform_setup(void);
void marvell_bl31_plat_runtime_setup(void);
void marvell_bl31_plat_arch_setup(void);
/* FIP TOC validity check */
int marvell_io_is_toc_valid(void);
/*
* PSCI functionality
*/
void marvell_psci_arch_init(int idx);
void plat_marvell_system_reset(void);
/*
* Optional functions required in Marvell standard platforms
*/
void plat_marvell_io_setup(void);
int plat_marvell_get_alt_image_source(
unsigned int image_id,
uintptr_t *dev_handle,
uintptr_t *image_spec);
unsigned int plat_marvell_calc_core_pos(u_register_t mpidr);
void plat_marvell_interconnect_init(void);
void plat_marvell_interconnect_enter_coherency(void);
const mmap_region_t *plat_marvell_get_mmap(void);
#endif /* __PLAT_MARVELL_H__ */
......@@ -45,7 +45,7 @@ spacer:
* Clobbers: x0 - x10, sp
* ---------------------------------------------
*/
.macro arm_print_gic_regs
.macro marvell_print_gic_regs
/* Check for GICv3 system register access */
mrs x7, id_aa64pfr0_el1
ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
......
......@@ -32,7 +32,8 @@
#define ROUND_UP_TO_POW_OF_2(number) (1 << \
(32 - __builtin_clz((number) - 1)))
#define _1MB_ (1024ULL*1024ULL)
#define _1GB_ (_1MB_*1024ULL)
#define _1MB_ (1024ULL * 1024ULL)
#define _1GB_ (_1MB_ * 1024ULL)
#define _2GB_ (2 * _1GB_)
#endif /* MVEBU_H */
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#include <a3700_pm.h>
#include <plat_marvell.h>
/* This struct provides the PM wake up src configuration */
static struct pm_wake_up_src_config wake_up_src_cfg = {
.wake_up_src_num = 3,
.wake_up_src[0] = {
.wake_up_src_type = WAKE_UP_SRC_GPIO,
.wake_up_data = {
.gpio_data.bank_num = 0, /* North Bridge */
.gpio_data.gpio_num = 14
}
},
.wake_up_src[1] = {
.wake_up_src_type = WAKE_UP_SRC_GPIO,
.wake_up_data = {
.gpio_data.bank_num = 1, /* South Bridge */
.gpio_data.gpio_num = 2
}
},
.wake_up_src[2] = {
.wake_up_src_type = WAKE_UP_SRC_UART1,
}
};
struct pm_wake_up_src_config *mv_wake_up_src_config_get(void)
{
return &wake_up_src_cfg;
}
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef __MVEBU_DEF_H__
#define __MVEBU_DEF_H__
#include <a3700_plat_def.h>
#endif /* __MVEBU_DEF_H__ */
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#include <armada_common.h>
#include <dram_win.h>
#include <io_addr_dec.h>
#include <mmio.h>
#include <marvell_plat_priv.h>
#include <plat_marvell.h>
/* This routine does MPP initialization */
static void marvell_bl31_mpp_init(void)
{
mmio_clrbits_32(MVEBU_NB_GPIO_SEL_REG, 1 << MVEBU_GPIO_TW1_GPIO_EN_OFF);
/* Set hidden GPIO setting for SPI.
* In north_bridge_pin_out_en_high register 13804,
* bit 28 is the one which enables CS, CLK pins to be
* output, need to set it to 1.
* The initial value of this bit is 1, but in UART boot mode
* initialization, this bit is disabled and the SPI CS and CLK pins
* are used for downloading image purpose; so after downloading,
* we should set this bit to 1 again to enable SPI CS and CLK pins.
* And anyway, this bit value should be 1 in all modes,
* so here we does not judge boot mode and set this bit to 1 always.
*/
mmio_setbits_32(MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG,
1 << MVEBU_GPIO_NB_SPI_PIN_MODE_OFF);
}
/* This function overruns the same function in marvell_bl31_setup.c */
void bl31_plat_arch_setup(void)
{
struct dec_win_config *io_dec_map;
uint32_t dec_win_num;
struct dram_win_map dram_wins_map;
marvell_bl31_plat_arch_setup();
/* MPP init */
marvell_bl31_mpp_init();
/* initialize the timer for delay functionality */
plat_delay_timer_init();
/* CPU address decoder windows initialization. */
cpu_wins_init();
/* fetch CPU-DRAM window mapping information by reading
* CPU-DRAM decode windows (only the enabled ones)
*/
dram_win_map_build(&dram_wins_map);
/* Get IO address decoder windows */
if (marvell_get_io_dec_win_conf(&io_dec_map, &dec_win_num)) {
printf("No IO address decoder windows configurations found!\n");
return;
}
/* IO address decoder init */
if (init_io_addr_dec(&dram_wins_map, io_dec_map, dec_win_num)) {
printf("IO address decoder windows initialization failed!\n");
return;
}
}
#
# Copyright (C) 2018 Marvell International Ltd.
#
# SPDX-License-Identifier: BSD-3-Clause
# https://spdx.org/licenses
#
include plat/marvell/a3700/common/a3700_common.mk
include plat/marvell/common/marvell_common.mk
#
# Copyright (C) 2018 Marvell International Ltd.
#
# SPDX-License-Identifier: BSD-3-Clause
# https://spdx.org/licenses
#
MARVELL_PLAT_BASE := plat/marvell
MARVELL_PLAT_INCLUDE_BASE := include/plat/marvell
PLAT_FAMILY := a3700
PLAT_FAMILY_BASE := $(MARVELL_PLAT_BASE)/$(PLAT_FAMILY)
PLAT_INCLUDE_BASE := $(MARVELL_PLAT_INCLUDE_BASE)/$(PLAT_FAMILY)
PLAT_COMMON_BASE := $(PLAT_FAMILY_BASE)/common
MARVELL_DRV_BASE := drivers/marvell
MARVELL_COMMON_BASE := $(MARVELL_PLAT_BASE)/common
include $(MARVELL_PLAT_BASE)/marvell.mk
#*********** A3700 *************
DOIMAGEPATH := $(WTP)
DOIMAGETOOL := $(DOIMAGEPATH)/wtptp/linux/tbb_linux
ifeq ($(MARVELL_SECURE_BOOT),1)
DOIMAGE_CFG := $(DOIMAGEPATH)/atf-tim.txt
IMAGESPATH := $(DOIMAGEPATH)/tim/trusted
TIMNCFG := $(DOIMAGEPATH)/atf-timN.txt
TIMNSIG := $(IMAGESPATH)/timnsign.txt
TIM2IMGARGS := -i $(DOIMAGE_CFG) -n $(TIMNCFG)
TIMN_IMAGE := $$(grep "Image Filename:" -m 1 $(TIMNCFG) | cut -c 17-)
else #MARVELL_SECURE_BOOT
DOIMAGE_CFG := $(DOIMAGEPATH)/atf-ntim.txt
IMAGESPATH := $(DOIMAGEPATH)/tim/untrusted
TIM2IMGARGS := -i $(DOIMAGE_CFG)
endif #MARVELL_SECURE_BOOT
TIMBUILD := $(DOIMAGEPATH)/script/buildtim.sh
TIM2IMG := $(DOIMAGEPATH)/script/tim2img.pl
# WTMI_IMG is used to specify the customized RTOS image running over
# Service CPU (CM3 processor). By the default, it points to a
# baremetal binary of fuse programming in A3700_utils.
WTMI_IMG := $(DOIMAGEPATH)/wtmi/fuse/build/fuse.bin
# WTMI_SYSINIT_IMG is used for the system early initialization,
# such as AVS settings, clock-tree setup and dynamic DDR PHY training.
# After the initialization is done, this image will be wiped out
# from the memory and CM3 will continue with RTOS image or other application.
WTMI_SYSINIT_IMG := $(DOIMAGEPATH)/wtmi/sys_init/build/sys_init.bin
# WTMI_MULTI_IMG is composed of CM3 RTOS image (WTMI_IMG)
# and sys-init image (WTMI_SYSINIT_IMG).
WTMI_MULTI_IMG := $(DOIMAGEPATH)/wtmi/build/wtmi.bin
WTMI_ENC_IMG := $(DOIMAGEPATH)/wtmi/build/wtmi-enc.bin
BUILD_UART := uart-images
SRCPATH := $(dir $(BL33))
CLOCKSPRESET ?= CPU_800_DDR_800
DDR_TOPOLOGY ?= 0
BOOTDEV ?= SPINOR
PARTNUM ?= 0
TIM_IMAGE := $$(grep "Image Filename:" -m 1 $(DOIMAGE_CFG) | cut -c 17-)
TIMBLDARGS := $(MARVELL_SECURE_BOOT) $(BOOTDEV) $(IMAGESPATH) $(DOIMAGEPATH) $(CLOCKSPRESET) \
$(DDR_TOPOLOGY) $(PARTNUM) $(DEBUG) $(DOIMAGE_CFG) $(TIMNCFG) $(TIMNSIG) 1
TIMBLDUARTARGS := $(MARVELL_SECURE_BOOT) UART $(IMAGESPATH) $(DOIMAGEPATH) $(CLOCKSPRESET) \
$(DDR_TOPOLOGY) 0 0 $(DOIMAGE_CFG) $(TIMNCFG) $(TIMNSIG) 0
DOIMAGE_FLAGS := -r $(DOIMAGE_CFG) -v -D
# GICV3
$(eval $(call add_define,CONFIG_GICV3))
# CCI-400
$(eval $(call add_define,USE_CCI))
MARVELL_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v3/gicv3_main.c \
drivers/arm/gic/v3/gicv3_helpers.c \
drivers/arm/gic/v3/arm_gicv3_common.c \
plat/common/plat_gicv3.c \
drivers/arm/gic/v3/gic500.c
ATF_INCLUDES := -Iinclude/common/tbbr \
-Iinclude/drivers