Commit 42a29337 authored by Grzegorz Jaszczyk's avatar Grzegorz Jaszczyk Committed by Konstantin Porotchkin
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mvebu: cp110: introduce COMPHY porting layer



Some of COMPHY parameters depends on the hw connection between the SoC
and the PHY, which can vary on different boards e.g. due to different
wires length. Define the "porting layer" with some defaults
parameters. It ease updating static values which needs to be updated due
to board differences, which are now grouped in one place.

Example porting layer for a8k-db is under:
plat/marvell/a8k/a80x0/board/phy-porting-layer.h

If for some boards parameters are not defined (missing
phy-porting-layer.h), the default values are used
(drivers/marvell/comphy/phy-default-porting-layer.h)
and the following compilation warning is show:
"Using default comphy params - you may need to suit them to your board".

The common COMPHY driver code is extracted in order to be shared with
future COMPHY driver for A3700 SoC platforms

Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: default avatarIgal Liberman <igall@marvell.com>
Signed-off-by: default avatarKonstantin Porotchkin <kostap@marvell.com>
parent 2b2c3f0a
.. _porting:
TF-A Porting Guide
=================
......@@ -64,3 +66,53 @@ Armada-70x0/Armada-80x0 Porting
- Please refer to '<path_to_mv_ddr_sources>/doc/porting_guide.txt' for detailed porting description.
- The build target directory is "build/<platform>/release/ble".
- Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h)
- Background:
Some of the comphy's parameters value depend on the HW connection between the SoC and the PHY. Every
board type has specific HW characteristics like wire length. Due to those differences some comphy
parameters vary between board types. Therefore each board type can have its own list of values for
all relevant comphy parameters. The PHY porting layer specifies which parameters need to be suited and
the board designer should provide relevant values.
.. seealso::
For XFI/SFI comphy type there is procedure "rx_training" which eases process of suiting some of
the parameters. Please see :ref:`uboot_cmd` section: rx_training.
The PHY porting layer simplifies updating static values per board type, which are now grouped in one place.
.. note::
The parameters for the same type of comphy may vary even for the same board type, it is because
the lanes from comphy-x to some PHY may have different HW characteristic than lanes from
comphy-y to the same (multiplexed) or other PHY.
- Porting:
The porting layer for PHY was introduced in TF-A. There is one file
``drivers/marvell/comphy/phy-default-porting-layer.h`` which contains the defaults. Those default
parameters are used only if there is no appropriate phy-porting-layer.h file under:
``plat/marvell/<soc family>/<platform>/board/phy-porting-layer.h``. If the phy-porting-layer.h exists,
the phy-default-porting-layer.h is not going to be included.
.. warning::
Not all comphy types are already reworked to support the PHY porting layer, currently the porting
layer is supported for XFI/SFI and SATA comphy types.
The easiest way to prepare the PHY porting layer for custom board is to copy existing example to a new
platform:
- cp ``plat/marvell/a8k/a80x0/board/phy-porting-layer.h`` "plat/marvell/<soc family>/<platform>/board/phy-porting-layer.h"
- adjust relevant parameters or
- if different comphy index is used for specific feature, move it to proper table entry and then adjust.
.. note::
The final table size with comphy parameters can be different, depending on the CP module count for
given SoC type.
- Example:
Example porting layer for armada-8040-db is under: ``plat/marvell/a8k/a80x0/board/phy-porting-layer.h``
.. note::
If there is no PHY porting layer for new platform (missing phy-porting-layer.h), the default
values are used (drivers/marvell/comphy/phy-default-porting-layer.h) and the user is warned:
.. warning::
"Using default comphy parameters - it may be required to suit them for your board".
......@@ -199,6 +199,11 @@
#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \
(0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
#define HPIPE_ADAPTED_DFE_COEFFICIENT_1_REG 0x30
#define HPIPE_ADAPTED_DFE_RES_OFFSET 13
#define HPIPE_ADAPTED_DFE_RES_MASK \
(0x3 << HPIPE_ADAPTED_DFE_RES_OFFSET)
#define HPIPE_G1_SET_0_REG 0x34
#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1
#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \
......@@ -326,6 +331,16 @@
#define HPIPE_PHY_TEST_DATA_MASK \
(0xffff << HPIPE_PHY_TEST_DATA_OFFSET)
#define HPIPE_PHY_TEST_PRBS_ERROR_COUNTER_1_REG 0x80
#define HPIPE_PHY_TEST_OOB_0_REGISTER 0x84
#define HPIPE_PHY_PT_OOB_EN_OFFSET 14
#define HPIPE_PHY_PT_OOB_EN_MASK \
(0x1 << HPIPE_PHY_PT_OOB_EN_OFFSET)
#define HPIPE_PHY_TEST_PT_TESTMODE_OFFSET 12
#define HPIPE_PHY_TEST_PT_TESTMODE_MASK \
(0x3 << HPIPE_PHY_TEST_PT_TESTMODE_OFFSET)
#define HPIPE_LOOPBACK_REG 0x8c
#define HPIPE_LOOPBACK_SEL_OFFSET 1
#define HPIPE_LOOPBACK_SEL_MASK \
......@@ -357,10 +372,27 @@
(0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET)
#define HPIPE_G2_SET_2_REG 0xf8
#define HPIPE_G2_SET_2_G2_TX_EMPH0_OFFSET 0
#define HPIPE_G2_SET_2_G2_TX_EMPH0_MASK \
(0xf << HPIPE_G2_SET_2_G2_TX_EMPH0_OFFSET)
#define HPIPE_G2_SET_2_G2_TX_EMPH0_EN_OFFSET 4
#define HPIPE_G2_SET_2_G2_TX_EMPH0_EN_MASK \
(0x1 << HPIPE_G2_SET_2_G2_TX_EMPH0_EN_OFFSET)
#define HPIPE_G2_TX_SSC_AMP_OFFSET 9
#define HPIPE_G2_TX_SSC_AMP_MASK \
(0x7f << HPIPE_G2_TX_SSC_AMP_OFFSET)
#define HPIPE_G3_SET_2_REG 0xfc
#define HPIPE_G3_SET_2_G3_TX_EMPH0_OFFSET 0
#define HPIPE_G3_SET_2_G3_TX_EMPH0_MASK \
(0xf << HPIPE_G3_SET_2_G3_TX_EMPH0_OFFSET)
#define HPIPE_G3_SET_2_G3_TX_EMPH0_EN_OFFSET 4
#define HPIPE_G3_SET_2_G3_TX_EMPH0_EN_MASK \
(0x1 << HPIPE_G3_SET_2_G3_TX_EMPH0_EN_OFFSET)
#define HPIPE_G3_TX_SSC_AMP_OFFSET 9
#define HPIPE_G3_TX_SSC_AMP_MASK \
(0x7f << HPIPE_G3_TX_SSC_AMP_OFFSET)
#define HPIPE_VDD_CAL_0_REG 0x108
#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15
#define HPIPE_CAL_VDD_CONT_MODE_MASK \
......@@ -434,6 +466,15 @@
#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \
(0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET)
/* HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIBRATION_CTRL_REG */
#define HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG 0x168
#define HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET 15
#define HPIPE_CAL_RXCLKALIGN_90_EXT_EN_MASK \
(0x1 << HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET)
#define HPIPE_CAL_OS_PH_EXT_OFFSET 8
#define HPIPE_CAL_OS_PH_EXT_MASK \
(0x7f << HPIPE_CAL_OS_PH_EXT_OFFSET)
#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6
#define HPIPE_RX_SAMPLER_OS_GAIN_MASK \
......@@ -484,6 +525,19 @@
#define HPIPE_OS_PH_VALID_MASK \
(0x1 << HPIPE_OS_PH_VALID_OFFSET)
#define HPIPE_DATA_PHASE_OFF_CTRL_REG 0x1A0
#define HPIPE_DATA_PHASE_ADAPTED_OS_PH_OFFSET 9
#define HPIPE_DATA_PHASE_ADAPTED_OS_PH_MASK \
(0x7f << HPIPE_DATA_PHASE_ADAPTED_OS_PH_OFFSET)
#define HPIPE_ADAPTED_FFE_CAPACITOR_COUNTER_CTRL_REG 0x1A4
#define HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_OFFSET 12
#define HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_MASK \
(0x3 << HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_OFFSET)
#define HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_OFFSET 8
#define HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_MASK \
(0xf << HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_OFFSET)
#define HPIPE_SQ_GLITCH_FILTER_CTRL 0x1c8
#define HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET 0
#define HPIPE_SQ_DEGLITCH_WIDTH_P_MASK \
......@@ -510,6 +564,26 @@
#define HPIPE_DME_ETHERNET_MODE_MASK \
(0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)
#define HPIPE_TRX_TRAIN_CTRL_0_REG 0x22c
#define HPIPE_TRX_TX_F0T_EO_BASED_OFFSET 14
#define HPIPE_TRX_TX_F0T_EO_BASED_MASK \
(1 << HPIPE_TRX_TX_F0T_EO_BASED_OFFSET)
#define HPIPE_TRX_UPDATE_THEN_HOLD_OFFSET 6
#define HPIPE_TRX_UPDATE_THEN_HOLD_MASK \
(1 << HPIPE_TRX_UPDATE_THEN_HOLD_OFFSET)
#define HPIPE_TRX_TX_CTRL_CLK_EN_OFFSET 5
#define HPIPE_TRX_TX_CTRL_CLK_EN_MASK \
(1 << HPIPE_TRX_TX_CTRL_CLK_EN_OFFSET)
#define HPIPE_TRX_RX_ANA_IF_CLK_ENE_OFFSET 4
#define HPIPE_TRX_RX_ANA_IF_CLK_ENE_MASK \
(1 << HPIPE_TRX_RX_ANA_IF_CLK_ENE_OFFSET)
#define HPIPE_TRX_TX_TRAIN_EN_OFFSET 1
#define HPIPE_TRX_TX_TRAIN_EN_MASK \
(1 << HPIPE_TRX_TX_TRAIN_EN_OFFSET)
#define HPIPE_TRX_RX_TRAIN_EN_OFFSET 0
#define HPIPE_TRX_RX_TRAIN_EN_MASK \
(1 << HPIPE_TRX_RX_TRAIN_EN_OFFSET)
#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \
......@@ -548,6 +622,23 @@
#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \
(0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
#define HPIPE_INTERRUPT_1_REGISTER 0x2AC
#define HPIPE_TRX_TRAIN_FAILED_OFFSET 6
#define HPIPE_TRX_TRAIN_FAILED_MASK \
(1 << HPIPE_TRX_TRAIN_FAILED_OFFSET)
#define HPIPE_TRX_TRAIN_TIME_OUT_INT_OFFSET 5
#define HPIPE_TRX_TRAIN_TIME_OUT_INT_MASK \
(1 << HPIPE_TRX_TRAIN_TIME_OUT_INT_OFFSET)
#define HPIPE_INTERRUPT_TRX_TRAIN_DONE_OFFSET 4
#define HPIPE_INTERRUPT_TRX_TRAIN_DONE_MASK \
(1 << HPIPE_INTERRUPT_TRX_TRAIN_DONE_OFFSET)
#define HPIPE_INTERRUPT_DFE_DONE_INT_OFFSET 3
#define HPIPE_INTERRUPT_DFE_DONE_INT_MASK \
(1 << HPIPE_INTERRUPT_DFE_DONE_INT_OFFSET)
#define HPIPE_INTERRUPT_RX_TRAIN_COMPLETE_INT_OFFSET 1
#define HPIPE_INTERRUPT_RX_TRAIN_COMPLETE_INT_MASK \
(1 << HPIPE_INTERRUPT_RX_TRAIN_COMPLETE_INT_OFFSET)
#define HPIPE_TX_TRAIN_REG 0x31C
#define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4
#define HPIPE_TX_TRAIN_CHK_INIT_MASK \
......
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
/* Marvell CP110 ana A3700 common */
#ifndef _PHY_COMPHY_COMMON_H
#define _PHY_COMPHY_COMMON_H
/* #define DEBUG_COMPHY */
#ifdef DEBUG_COMPHY
#define debug(format...) printf(format)
#else
#define debug(format, arg...)
#endif
/* A lane is described by 4 fields:
* - bit 1~0 represent comphy polarity invert
* - bit 7~2 represent comphy speed
* - bit 11~8 represent unit index
* - bit 16~12 represent mode
* - bit 17 represent comphy indication of clock source
* - bit 19-18 represents pcie width (in case of pcie comphy config.)
* - bit 31~20 reserved
*/
#define COMPHY_INVERT_OFFSET 0
#define COMPHY_INVERT_LEN 2
#define COMPHY_INVERT_MASK COMPHY_MASK(COMPHY_INVERT_OFFSET, \
COMPHY_INVERT_LEN)
#define COMPHY_SPEED_OFFSET (COMPHY_INVERT_OFFSET + COMPHY_INVERT_LEN)
#define COMPHY_SPEED_LEN 6
#define COMPHY_SPEED_MASK COMPHY_MASK(COMPHY_SPEED_OFFSET, \
COMPHY_SPEED_LEN)
#define COMPHY_UNIT_ID_OFFSET (COMPHY_SPEED_OFFSET + COMPHY_SPEED_LEN)
#define COMPHY_UNIT_ID_LEN 4
#define COMPHY_UNIT_ID_MASK COMPHY_MASK(COMPHY_UNIT_ID_OFFSET, \
COMPHY_UNIT_ID_LEN)
#define COMPHY_MODE_OFFSET (COMPHY_UNIT_ID_OFFSET + COMPHY_UNIT_ID_LEN)
#define COMPHY_MODE_LEN 5
#define COMPHY_MODE_MASK COMPHY_MASK(COMPHY_MODE_OFFSET, COMPHY_MODE_LEN)
#define COMPHY_CLK_SRC_OFFSET (COMPHY_MODE_OFFSET + COMPHY_MODE_LEN)
#define COMPHY_CLK_SRC_LEN 1
#define COMPHY_CLK_SRC_MASK COMPHY_MASK(COMPHY_CLK_SRC_OFFSET, \
COMPHY_CLK_SRC_LEN)
#define COMPHY_PCI_WIDTH_OFFSET (COMPHY_CLK_SRC_OFFSET + COMPHY_CLK_SRC_LEN)
#define COMPHY_PCI_WIDTH_LEN 3
#define COMPHY_PCI_WIDTH_MASK COMPHY_MASK(COMPHY_PCI_WIDTH_OFFSET, \
COMPHY_PCI_WIDTH_LEN)
#define COMPHY_MASK(offset, len) (((1 << (len)) - 1) << (offset))
/* Macro which extracts mode from lane description */
#define COMPHY_GET_MODE(x) (((x) & COMPHY_MODE_MASK) >> \
COMPHY_MODE_OFFSET)
/* Macro which extracts unit index from lane description */
#define COMPHY_GET_ID(x) (((x) & COMPHY_UNIT_ID_MASK) >> \
COMPHY_UNIT_ID_OFFSET)
/* Macro which extracts speed from lane description */
#define COMPHY_GET_SPEED(x) (((x) & COMPHY_SPEED_MASK) >> \
COMPHY_SPEED_OFFSET)
/* Macro which extracts clock source indication from lane description */
#define COMPHY_GET_CLK_SRC(x) (((x) & COMPHY_CLK_SRC_MASK) >> \
COMPHY_CLK_SRC_OFFSET)
/* Macro which extracts pcie width indication from lane description */
#define COMPHY_GET_PCIE_WIDTH(x) (((x) & COMPHY_PCI_WIDTH_MASK) >> \
COMPHY_PCI_WIDTH_OFFSET)
/* Macro which extracts the polarity invert from lane description */
#define COMPHY_GET_POLARITY_INVERT(x) (((x) & COMPHY_INVERT_MASK) >> \
COMPHY_INVERT_OFFSET)
#define COMPHY_SATA_MODE 0x1
#define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */
#define COMPHY_HS_SGMII_MODE 0x3 /* SGMII 2.5G */
#define COMPHY_USB3H_MODE 0x4
#define COMPHY_USB3D_MODE 0x5
#define COMPHY_PCIE_MODE 0x6
#define COMPHY_RXAUI_MODE 0x7
#define COMPHY_XFI_MODE 0x8
#define COMPHY_SFI_MODE 0x9
#define COMPHY_USB3_MODE 0xa
#define COMPHY_AP_MODE 0xb
#define COMPHY_UNUSED 0xFFFFFFFF
/* Polarity invert macro */
#define COMPHY_POLARITY_NO_INVERT 0
#define COMPHY_POLARITY_TXD_INVERT 1
#define COMPHY_POLARITY_RXD_INVERT 2
#define COMPHY_POLARITY_ALL_INVERT (COMPHY_POLARITY_TXD_INVERT | \
COMPHY_POLARITY_RXD_INVERT)
enum reg_width_type {
REG_16BIT = 0,
REG_32BIT,
};
enum {
COMPHY_LANE0 = 0,
COMPHY_LANE1,
COMPHY_LANE2,
COMPHY_LANE3,
COMPHY_LANE4,
COMPHY_LANE5,
COMPHY_LANE_MAX,
};
static inline uint32_t polling_with_timeout(uintptr_t addr, uint32_t val,
uint32_t mask,
uint32_t usec_timeout,
enum reg_width_type type)
{
uint32_t data;
do {
udelay(1);
if (type == REG_16BIT)
data = mmio_read_16(addr) & mask;
else
data = mmio_read_32(addr) & mask;
} while (data != val && --usec_timeout > 0);
if (usec_timeout == 0)
return data;
return 0;
}
static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask)
{
debug("<atf>: WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ",
addr, data, mask);
debug("old value = 0x%x ==> ", mmio_read_32(addr));
mmio_clrsetbits_32(addr, mask, data);
debug("new val 0x%x\n", mmio_read_32(addr));
}
static inline void __unused reg_set16(uintptr_t addr, uint16_t data,
uint16_t mask)
{
debug("<atf>: WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ",
addr, data, mask);
debug("old value = 0x%x ==> ", mmio_read_16(addr));
mmio_clrsetbits_16(addr, mask, data);
debug("new val 0x%x\n", mmio_read_16(addr));
}
#endif /* _PHY_COMPHY_COMMON_H */
This diff is collapsed.
......@@ -5,7 +5,79 @@
* https://spdx.org/licenses
*/
/* Marvell CP110 SoC COMPHY unit driver */
/* Those are parameters for xfi mode, which need to be tune for each board type.
* For known DB boards the parameters was already calibrated and placed under
* the plat/marvell/a8k/<board_type>/board/phy-porting-layer.h
*/
struct xfi_params {
uint8_t g1_ffe_res_sel;
uint8_t g1_ffe_cap_sel;
uint8_t align90;
uint8_t g1_dfe_res;
uint8_t g1_amp;
uint8_t g1_emph;
uint8_t g1_emph_en;
uint8_t g1_tx_amp_adj;
uint8_t g1_tx_emph_en;
uint8_t g1_tx_emph;
uint8_t g1_rx_selmuff;
uint8_t g1_rx_selmufi;
uint8_t g1_rx_selmupf;
uint8_t g1_rx_selmupi;
_Bool valid;
};
struct sata_params {
uint8_t g1_amp;
uint8_t g2_amp;
uint8_t g3_amp;
uint8_t g1_emph;
uint8_t g2_emph;
uint8_t g3_emph;
uint8_t g1_emph_en;
uint8_t g2_emph_en;
uint8_t g3_emph_en;
uint8_t g1_tx_amp_adj;
uint8_t g2_tx_amp_adj;
uint8_t g3_tx_amp_adj;
uint8_t g1_tx_emph_en;
uint8_t g2_tx_emph_en;
uint8_t g3_tx_emph_en;
uint8_t g1_tx_emph;
uint8_t g2_tx_emph;
uint8_t g3_tx_emph;
uint8_t g3_dfe_res;
uint8_t g3_ffe_res_sel;
uint8_t g3_ffe_cap_sel;
uint8_t align90;
uint8_t g1_rx_selmuff;
uint8_t g2_rx_selmuff;
uint8_t g3_rx_selmuff;
uint8_t g1_rx_selmufi;
uint8_t g2_rx_selmufi;
uint8_t g3_rx_selmufi;
uint8_t g1_rx_selmupf;
uint8_t g2_rx_selmupf;
uint8_t g3_rx_selmupf;
uint8_t g1_rx_selmupi;
uint8_t g2_rx_selmupi;
uint8_t g3_rx_selmupi;
_Bool valid;
};
int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base,
uint8_t comphy_index);
......
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef __PHY_DEFAULT_PORTING_LAYER_H
#define __PHY_DEFAULT_PORTING_LAYER_H
#define MAX_LANE_NR 6
#warning "Using default comphy params - you may need to suit them to your board"
static const struct xfi_params
xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
.g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, .align90 = 0x5f,
.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1, .g1_tx_emph_en = 0x1,
.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2, .valid = 1
}
};
static const struct sata_params
sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
.g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
.g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1,
.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
.g3_tx_amp_adj = 0x1,
.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
.g3_tx_emph_en = 0x0,
.g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1,
.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf,
.align90 = 0x61,
.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
.g3_rx_selmuff = 0x3,
.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
.g3_rx_selmufi = 0x3,
.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
.valid = 0x1
},
};
#endif /* __PHY_DEFAULT_PORTING_LAYER_H */
......@@ -7,6 +7,9 @@
PCI_EP_SUPPORT := 0
CP_NUM := 1
$(eval $(call add_define,CP_NUM))
DOIMAGE_SEC := tools/doimage/secure/sec_img_7K.cfg
MARVELL_MOCHI_DRV := drivers/marvell/mochi/apn806_setup.c
......
......@@ -7,6 +7,9 @@
PCI_EP_SUPPORT := 0
CP_NUM := 1
$(eval $(call add_define,CP_NUM))
DOIMAGE_SEC := tools/doimage/secure/sec_img_7K.cfg
MARVELL_MOCHI_DRV := drivers/marvell/mochi/apn806_setup.c
......
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef __PHY_PORTING_LAYER_H
#define __PHY_PORTING_LAYER_H
#define MAX_LANE_NR 6
static const struct xfi_params
xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
/* AP0 */
{
/* CP 0 */
{
{ 0 }, /* Comphy0 */
{ 0 }, /* Comphy1 */
{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
.align90 = 0x5f,
.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
.g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
.g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
.valid = 0x1 }, /* Comphy2 */
{ 0 }, /* Comphy3 */
{ 0 }, /* Comphy4 */
{ 0 }, /* Comphy5 */
},
/* CP 1 */
{
{ 0 }, /* Comphy0 */
{ 0 }, /* Comphy1 */
{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
.align90 = 0x5f,
.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
.g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
.g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
.valid = 0x1 }, /* Comphy2 */
{ 0 }, /* Comphy3 */
{ 0 }, /* Comphy4 */
{ 0 }, /* Comphy5 */
},
},
};
static const struct sata_params
sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
/* AP0 */
{
/* CP 0 */
{
{ 0 }, /* Comphy0 */
{ .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
.g1_emph_en = 0x1, .g2_emph_en = 0x1,
.g3_emph_en = 0x1,
.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
.g3_tx_amp_adj = 0x1,
.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
.g3_tx_emph_en = 0x0,
.g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
.g3_tx_emph = 0x1,
.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
.g3_ffe_cap_sel = 0xf,
.align90 = 0x61,
.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
.g3_rx_selmuff = 0x3,
.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
.g3_rx_selmufi = 0x3,
.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
.valid = 0x1
}, /* Comphy1 */
{ 0 }, /* Comphy2 */
{ .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
.g1_emph_en = 0x1, .g2_emph_en = 0x1,
.g3_emph_en = 0x1,
.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
.g3_tx_amp_adj = 0x1,
.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
.g3_tx_emph_en = 0x0,
.g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
.g3_tx_emph = 0x1,
.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
.g3_ffe_cap_sel = 0xf,
.align90 = 0x61,
.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,