Commit 486f868b authored by Konstantin Porotchkin's avatar Konstantin Porotchkin
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plat: marvell: Add common ARMADA platform components



Add common Marvell ARMADA platform components.
This patch also includes common components for Marvell
ARMADA 8K platforms.

Change-Id: I42192fdc6525a42e46b3ac2ad63c83db9bcbfeaf
Signed-off-by: default avatarHanna Hawa <hannah@marvell.com>
Signed-off-by: default avatarKonstantin Porotchkin <kostap@marvell.com>
parent 939e0856
/*
* Copyright (C) 2017 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef _ARO_H_
#define _ARO_H_
enum hws_freq {
CPU_FREQ_2000,
CPU_FREQ_1800,
CPU_FREQ_1600,
CPU_FREQ_1400,
CPU_FREQ_1300,
CPU_FREQ_1200,
CPU_FREQ_1000,
CPU_FREQ_600,
CPU_FREQ_800,
DDR_FREQ_LAST,
DDR_FREQ_SAR
};
enum cpu_clock_freq_mode {
CPU_2000_DDR_1200_RCLK_1200 = 0x0,
CPU_2000_DDR_1050_RCLK_1050 = 0x1,
CPU_1600_DDR_800_RCLK_800 = 0x4,
CPU_1800_DDR_1200_RCLK_1200 = 0x6,
CPU_1800_DDR_1050_RCLK_1050 = 0x7,
CPU_1600_DDR_900_RCLK_900 = 0x0B,
CPU_1600_DDR_1050_RCLK_1050 = 0x0D,
CPU_1600_DDR_900_RCLK_900_2 = 0x0E,
CPU_1000_DDR_650_RCLK_650 = 0x13,
CPU_1300_DDR_800_RCLK_800 = 0x14,
CPU_1300_DDR_650_RCLK_650 = 0x17,
CPU_1200_DDR_800_RCLK_800 = 0x19,
CPU_1400_DDR_800_RCLK_800 = 0x1a,
CPU_600_DDR_800_RCLK_800 = 0x1B,
CPU_800_DDR_800_RCLK_800 = 0x1C,
CPU_1000_DDR_800_RCLK_800 = 0x1D,
CPU_DDR_RCLK_INVALID
};
int init_aro(void);
#endif /* _ARO_H_ */
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef __A8K_COMMON_H__
#define __A8K_COMMON_H__
#include <amb_adec.h>
#include <io_win.h>
#include <iob.h>
#include <ccu.h>
/*
* This struct supports skip image request
* detection_method: the method used to detect the request "signal".
* info:
* GPIO:
* detection_method: HIGH (pressed button), LOW (unpressed button),
* num (button mpp number).
* i2c:
* i2c_addr: the address of the i2c chosen.
* i2d_reg: the i2c register chosen.
* test:
* choose the DIE you picked the button in (AP or CP).
* in case of CP(cp_index = 0 if CP0, cp_index = 1 if CP1)
*/
struct skip_image {
enum {
GPIO,
I2C,
USER_DEFINED
} detection_method;
struct {
struct {
int num;
enum {
HIGH,
LOW
} button_state;
} gpio;
struct {
int i2c_addr;
int i2c_reg;
} i2c;
struct {
enum {
CP,
AP
} cp_ap;
int cp_index;
} test;
} info;
};
/*
* This struct supports SoC power off method
* type: the method used to power off the SoC
* cfg:
* PMIC_GPIO:
* pin_count: current GPIO pin number used for toggling the signal for
* notifying external PMIC
* info: holds the GPIOs information, CP GPIO should be used and
* all GPIOs should be within same GPIO config. register
* step_count: current step number to toggle the GPIO for PMIC
* seq: GPIO toggling values in sequence, each bit represents a GPIO.
* For example, bit0 represents first GPIO used for toggling
* the GPIO the last step is used to trigger the power off
* signal
* delay_ms: transition interval for the GPIO setting to take effect
* in unit of ms
*/
/* Max GPIO number used to notify PMIC to power off the SoC */
#define PMIC_GPIO_MAX_NUMBER 8
/* Max GPIO toggling steps in sequence to power off the SoC */
#define PMIC_GPIO_MAX_TOGGLE_STEP 8
enum gpio_output_state {
GPIO_LOW = 0,
GPIO_HIGH
};
typedef struct gpio_info {
int cp_index;
int gpio_index;
} gpio_info_t;
struct power_off_method {
enum {
PMIC_GPIO,
} type;
struct {
struct {
int pin_count;
struct gpio_info info[PMIC_GPIO_MAX_NUMBER];
int step_count;
uint32_t seq[PMIC_GPIO_MAX_TOGGLE_STEP];
int delay_ms;
} gpio;
} cfg;
};
int marvell_gpio_config(void);
uint32_t marvell_get_io_win_gcr_target(int ap_idx);
uint32_t marvell_get_ccu_gcr_target(int ap_idx);
/*
* The functions below are defined as Weak and may be overridden
* in specific Marvell standard platform
*/
int marvell_get_amb_memory_map(struct addr_map_win **win,
uint32_t *size, uintptr_t base);
int marvell_get_io_win_memory_map(int ap_idx, struct addr_map_win **win,
uint32_t *size);
int marvell_get_iob_memory_map(struct addr_map_win **win,
uint32_t *size, uintptr_t base);
int marvell_get_ccu_memory_map(int ap_idx, struct addr_map_win **win,
uint32_t *size);
#endif /* __A8K_COMMON_H__ */
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef __BOARD_MARVELL_DEF_H__
#define __BOARD_MARVELL_DEF_H__
/*
* Required platform porting definitions common to all ARM
* development platforms
*/
/* Size of cacheable stacks */
#if DEBUG_XLAT_TABLE
# define PLATFORM_STACK_SIZE 0x800
#elif IMAGE_BL1
#if TRUSTED_BOARD_BOOT
# define PLATFORM_STACK_SIZE 0x1000
#else
# define PLATFORM_STACK_SIZE 0x440
#endif
#elif IMAGE_BL2
# if TRUSTED_BOARD_BOOT
# define PLATFORM_STACK_SIZE 0x1000
# else
# define PLATFORM_STACK_SIZE 0x400
# endif
#elif IMAGE_BL31
# define PLATFORM_STACK_SIZE 0x400
#elif IMAGE_BL32
# define PLATFORM_STACK_SIZE 0x440
#endif
/*
* PLAT_MARVELL_MMAP_ENTRIES depends on the number of entries in the
* plat_arm_mmap array defined for each BL stage.
*/
#if IMAGE_BLE
# define PLAT_MARVELL_MMAP_ENTRIES 3
#endif
#if IMAGE_BL1
# if TRUSTED_BOARD_BOOT
# define PLAT_MARVELL_MMAP_ENTRIES 7
# else
# define PLAT_MARVELL_MMAP_ENTRIES 6
# endif /* TRUSTED_BOARD_BOOT */
#endif
#if IMAGE_BL2
# define PLAT_MARVELL_MMAP_ENTRIES 8
#endif
#if IMAGE_BL31
#define PLAT_MARVELL_MMAP_ENTRIES 5
#endif
/*
* Platform specific page table and MMU setup constants
*/
#if IMAGE_BL1
#define MAX_XLAT_TABLES 4
#elif IMAGE_BLE
# define MAX_XLAT_TABLES 4
#elif IMAGE_BL2
# define MAX_XLAT_TABLES 4
#elif IMAGE_BL31
# define MAX_XLAT_TABLES 4
#elif IMAGE_BL32
# define MAX_XLAT_TABLES 4
#endif
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
#define PLAT_MARVELL_TRUSTED_SRAM_SIZE 0x80000 /* 512 KB */
#endif /* __BOARD_MARVELL_DEF_H__ */
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef __MARVELL_DEF_H__
#define __MARVELL_DEF_H__
#include <arch.h>
#include <common_def.h>
#include <platform_def.h>
#include <tbbr_img_def.h>
#include <xlat_tables.h>
/******************************************************************************
* Definitions common to all MARVELL standard platforms
*****************************************************************************/
/* Special value used to verify platform parameters from BL2 to BL31 */
#define MARVELL_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
#define MARVELL_CACHE_WRITEBACK_SHIFT 6
/*
* Macros mapping the MPIDR Affinity levels to MARVELL Platform Power levels.
* The power levels have a 1:1 mapping with the MPIDR affinity levels.
*/
#define MARVELL_PWR_LVL0 MPIDR_AFFLVL0
#define MARVELL_PWR_LVL1 MPIDR_AFFLVL1
#define MARVELL_PWR_LVL2 MPIDR_AFFLVL2
/*
* Macros for local power states in Marvell platforms encoded by
* State-ID field within the power-state parameter.
*/
/* Local power state for power domains in Run state. */
#define MARVELL_LOCAL_STATE_RUN 0
/* Local power state for retention. Valid only for CPU power domains */
#define MARVELL_LOCAL_STATE_RET 1
/*
* Local power state for OFF/power-down. Valid for CPU
* and cluster power domains
*/
#define MARVELL_LOCAL_STATE_OFF 2
/* The first 4KB of Trusted SRAM are used as shared memory */
#define MARVELL_TRUSTED_SRAM_BASE PLAT_MARVELL_ATF_BASE
#define MARVELL_SHARED_RAM_BASE MARVELL_TRUSTED_SRAM_BASE
#define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
/* The remaining Trusted SRAM is used to load the BL images */
#define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \
MARVELL_SHARED_RAM_SIZE)
#define MARVELL_BL_RAM_SIZE (PLAT_MARVELL_TRUSTED_SRAM_SIZE - \
MARVELL_SHARED_RAM_SIZE)
/* Non-shared DRAM */
#define MARVELL_DRAM_BASE ULL(0x0)
#define MARVELL_DRAM_SIZE ULL(0x80000000)
#define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \
MARVELL_DRAM_SIZE - 1)
#define MARVELL_IRQ_SEC_PHY_TIMER 29
#define MARVELL_IRQ_SEC_SGI_0 8
#define MARVELL_IRQ_SEC_SGI_1 9
#define MARVELL_IRQ_SEC_SGI_2 10
#define MARVELL_IRQ_SEC_SGI_3 11
#define MARVELL_IRQ_SEC_SGI_4 12
#define MARVELL_IRQ_SEC_SGI_5 13
#define MARVELL_IRQ_SEC_SGI_6 14
#define MARVELL_IRQ_SEC_SGI_7 15
#define MARVELL_MAP_SHARED_RAM MAP_REGION_FLAT( \
MARVELL_SHARED_RAM_BASE,\
MARVELL_SHARED_RAM_SIZE,\
MT_MEMORY | MT_RW | MT_SECURE)
#define MARVELL_MAP_DRAM MAP_REGION_FLAT( \
MARVELL_DRAM_BASE, \
MARVELL_DRAM_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
/*
* The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
#if USE_COHERENT_MEM
#define MARVELL_BL_REGIONS 3
#else
#define MARVELL_BL_REGIONS 2
#endif
#define MAX_MMAP_REGIONS (PLAT_MARVELL_MMAP_ENTRIES + \
MARVELL_BL_REGIONS)
#define MARVELL_CONSOLE_BAUDRATE 115200
/******************************************************************************
* Required platform porting definitions common to all MARVELL std. platforms
*****************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
/*
* This macro defines the deepest retention state possible. A higher state
* id will represent an invalid or a power down state.
*/
#define PLAT_MAX_RET_STATE MARVELL_LOCAL_STATE_RET
/*
* This macro defines the deepest power down states possible. Any state ID
* higher than this is invalid.
*/
#define PLAT_MAX_OFF_STATE MARVELL_LOCAL_STATE_OFF
#define PLATFORM_CORE_COUNT PLAT_MARVELL_CORE_COUNT
#define PLAT_NUM_PWR_DOMAINS (PLAT_MARVELL_CLUSTER_COUNT + \
PLATFORM_CORE_COUNT)
/*
* Some data must be aligned on the biggest cache line size in the platform.
* This is known only to the platform as it might have a combination of
* integrated and external caches.
*/
#define CACHE_WRITEBACK_GRANULE (1 << MARVELL_CACHE_WRITEBACK_SHIFT)
/*******************************************************************************
* BL1 specific defines.
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
* addresses.
******************************************************************************/
#define BL1_RO_BASE PLAT_MARVELL_TRUSTED_ROM_BASE
#define BL1_RO_LIMIT (PLAT_MARVELL_TRUSTED_ROM_BASE \
+ PLAT_MARVELL_TRUSTED_ROM_SIZE)
/*
* Put BL1 RW at the top of the Trusted SRAM.
*/
#define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \
MARVELL_BL_RAM_SIZE - \
PLAT_MARVELL_MAX_BL1_RW_SIZE)
#define BL1_RW_LIMIT (MARVELL_BL_RAM_BASE + MARVELL_BL_RAM_SIZE)
/*******************************************************************************
* BLE specific defines.
******************************************************************************/
#define BLE_BASE PLAT_MARVELL_SRAM_BASE
#define BLE_LIMIT PLAT_MARVELL_SRAM_END
/*******************************************************************************
* BL2 specific defines.
******************************************************************************/
/*
* Put BL2 just below BL31.
*/
#define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE)
#define BL2_LIMIT BL31_BASE
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
/*
* Put BL31 at the top of the Trusted SRAM.
*/
#define BL31_BASE (MARVELL_BL_RAM_BASE + \
MARVELL_BL_RAM_SIZE - \
PLAT_MARVEL_MAX_BL31_SIZE)
#define BL31_PROGBITS_LIMIT BL1_RW_BASE
#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \
MARVELL_BL_RAM_SIZE)
#endif /* __MARVELL_DEF_H__ */
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef __PLAT_MARVELL_H__
#define __PLAT_MARVELL_H__
#include <cassert.h>
#include <cpu_data.h>
#include <stdint.h>
#include <utils.h>
#include <xlat_tables.h>
/*
* Extern declarations common to Marvell standard platforms
*/
extern const mmap_region_t plat_marvell_mmap[];
#define MARVELL_CASSERT_MMAP \
CASSERT((ARRAY_SIZE(plat_marvell_mmap) + MARVELL_BL_REGIONS) \
<= MAX_MMAP_REGIONS, \
assert_max_mmap_regions)
/*
* Utility functions common to Marvell standard platforms
*/
void marvell_setup_page_tables(uintptr_t total_base,
size_t total_size,
uintptr_t code_start,
uintptr_t code_limit,
uintptr_t rodata_start,
uintptr_t rodata_limit
#if USE_COHERENT_MEM
, uintptr_t coh_start,
uintptr_t coh_limit
#endif
);
/* IO storage utility functions */
void marvell_io_setup(void);
/* Systimer utility function */
void marvell_configure_sys_timer(void);
/* Topology utility function */
int marvell_check_mpidr(u_register_t mpidr);
/* BLE utility functions */
int ble_plat_setup(int *skip);
void plat_marvell_dram_update_topology(void);
void ble_plat_pcie_ep_setup(void);
struct pci_hw_cfg *plat_get_pcie_hw_data(void);
/* BL1 utility functions */
void marvell_bl1_early_platform_setup(void);
void marvell_bl1_platform_setup(void);
void marvell_bl1_plat_arch_setup(void);
/* BL2 utility functions */
void marvell_bl2_early_platform_setup(meminfo_t *mem_layout);
void marvell_bl2_platform_setup(void);
void marvell_bl2_plat_arch_setup(void);
uint32_t marvell_get_spsr_for_bl32_entry(void);
uint32_t marvell_get_spsr_for_bl33_entry(void);
/* BL31 utility functions */
void marvell_bl31_early_platform_setup(bl31_params_t *from_bl2,
void *plat_params_from_bl2);
void marvell_bl31_platform_setup(void);
void marvell_bl31_plat_runtime_setup(void);
void marvell_bl31_plat_arch_setup(void);
/* Power management config to power off the SoC */
void *plat_marvell_get_pm_cfg(void);
/* Check if MSS AP CM3 firmware contains PM support */
_Bool is_pm_fw_running(void);
/* Bootrom image recovery utility functions */
void *plat_marvell_get_skip_image_data(void);
/* FIP TOC validity check */
int marvell_io_is_toc_valid(void);
/*
* PSCI functionality
*/
void marvell_psci_arch_init(int ap_idx);
void plat_marvell_system_reset(void);
/*
* Optional functions required in Marvell standard platforms
*/
void plat_marvell_io_setup(void);
int plat_marvell_get_alt_image_source(
unsigned int image_id,
uintptr_t *dev_handle,
uintptr_t *image_spec);
unsigned int plat_marvell_calc_core_pos(u_register_t mpidr);
const mmap_region_t *plat_marvell_get_mmap(void);
void marvell_ble_prepare_exit(void);
void marvell_exit_bootrom(uintptr_t base);
int plat_marvell_early_cpu_powerdown(void);
#endif /* __PLAT_MARVELL_H__ */
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#ifndef __PLAT_PM_TRACE_H
#define __PLAT_PM_TRACE_H
/*
* PM Trace is for Debug purpose only!!!
* It should not be enabled during System Run time
*/
#undef PM_TRACE_ENABLE
/* trace entry time */
struct pm_trace_entry {
/* trace entry time stamp */
unsigned int timestamp;
/* trace info
* [16-31] - API Trace Id
* [00-15] - API Step Id
*/
unsigned int trace_info;
};
struct pm_trace_ctrl {
/* trace pointer - points to next free entry in trace cyclic queue */
unsigned int trace_pointer;
/* trace count - number of entries in the queue, clear upon read */
unsigned int trace_count;
};
/* trace size definition */
#define AP_MSS_ATF_CORE_INFO_SIZE (256)
#define AP_MSS_ATF_CORE_ENTRY_SIZE (8)
#define AP_MSS_ATF_TRACE_SIZE_MASK (0xFF)
/* trace address definition */
#define AP_MSS_TIMER_BASE (MVEBU_REGS_BASE_MASK + 0x580110)
#define AP_MSS_ATF_CORE_0_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x520140)
#define AP_MSS_ATF_CORE_1_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x520150)
#define AP_MSS_ATF_CORE_2_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x520160)
#define AP_MSS_ATF_CORE_3_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x520170)
#define AP_MSS_ATF_CORE_CTRL_BASE (AP_MSS_ATF_CORE_0_CTRL_BASE)
#define AP_MSS_ATF_CORE_0_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5201C0)
#define AP_MSS_ATF_CORE_0_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5201C4)
#define AP_MSS_ATF_CORE_1_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5209C0)
#define AP_MSS_ATF_CORE_1_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5209C4)
#define AP_MSS_ATF_CORE_2_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5211C0)
#define AP_MSS_ATF_CORE_2_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5211C4)
#define AP_MSS_ATF_CORE_3_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5219C0)
#define AP_MSS_ATF_CORE_3_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5219C4)
#define AP_MSS_ATF_CORE_INFO_BASE (AP_MSS_ATF_CORE_0_INFO_BASE)
/* trace info definition */
#define TRACE_PWR_DOMAIN_OFF (0x10000)
#define TRACE_PWR_DOMAIN_SUSPEND (0x20000)
#define TRACE_PWR_DOMAIN_SUSPEND_FINISH (0x30000)
#define TRACE_PWR_DOMAIN_ON (0x40000)
#define TRACE_PWR_DOMAIN_ON_FINISH (0x50000)
#define TRACE_PWR_DOMAIN_ON_MASK (0xFF)