Commit a2847172 authored by Grzegorz Jaszczyk's avatar Grzegorz Jaszczyk Committed by Marcin Wojtas
Browse files

marvell: armada: add extra level in marvell platform hierarchy



This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
plat, include/plat) are moved to the new "armada" sub-folder.

Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655
Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: default avatarMarcin Wojtas <mw@semihalf.com>
parent 967a6d16
......@@ -84,7 +84,7 @@ There are several build options:
- BLE_PATH
Points to BLE (Binary ROM extension) sources folder. Only required for A8K builds.
The parameter is optional, its default value is ``plat/marvell/a8k/common/ble``.
The parameter is optional, its default value is ``plat/marvell/armada/a8k/common/ble``.
- MV_DDR_PATH
......@@ -192,7 +192,7 @@ Special Build Flags
In order to build UART recovery image this operation should be disabled for
a70x0 and a80x0 because of hardware limitation (boot from secondary image
can interrupt UART recovery process). This MACRO definition is set in
``plat/marvell/a8k/common/include/platform_def.h`` file.
``plat/marvell/armada/a8k/common/include/platform_def.h`` file.
For more information about build options, please refer to the
:ref:`Build Options` document.
......
......@@ -8,13 +8,13 @@ SoC being used is already supported in TF-A.
Source Code Structure
---------------------
- The customer platform specific code shall reside under ``plat/marvell/<soc family>/<soc>_cust``
(e.g. 'plat/marvell/a8k/a7040_cust').
- The customer platform specific code shall reside under ``plat/marvell/armada/<soc family>/<soc>_cust``
(e.g. 'plat/marvell/armada/a8k/a7040_cust').
- The platform name for build purposes is called ``<soc>_cust`` (e.g. ``a7040_cust``).
- The build system will reuse all files from within the soc directory, and take only the porting
files from the customer platform directory.
Files that require porting are located at ``plat/marvell/<soc family>/<soc>_cust`` directory.
Files that require porting are located at ``plat/marvell/armada/<soc family>/<soc>_cust`` directory.
Armada-70x0/Armada-80x0 Porting
......@@ -64,7 +64,7 @@ boot loader recovery (marvell_plat_config.c)
- Example:
In A7040-DB specific implementation
(``plat/marvell/a8k/a70x0/board/marvell_plat_config.c``), the image skip is
(``plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c``), the image skip is
implemented using GPIO: mpp 33 (SW5).
Before resetting the board make sure there is a valid image on the next flash
......@@ -91,7 +91,7 @@ The BLE and consequently, the DDR init code is executed at the early stage of
the boot process.
Each supported platform of the TF-A has its own DDR porting file called
dram_port.c located at ``atf/plat/marvell/a8k/<platform>/board`` directory.
dram_port.c located at ``atf/plat/marvell/armada/a8k/<platform>/board`` directory.
Please refer to '<path_to_mv_ddr_sources>/doc/porting_guide.txt' for detailed
porting description.
......@@ -128,7 +128,7 @@ Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h)
The porting layer for PHY was introduced in TF-A. There is one file
``drivers/marvell/comphy/phy-default-porting-layer.h`` which contains the
defaults. Those default parameters are used only if there is no appropriate
phy-porting-layer.h file under: ``plat/marvell/<soc
phy-porting-layer.h file under: ``plat/marvell/armada/<soc
family>/<platform>/board/phy-porting-layer.h``. If the phy-porting-layer.h
exists, the phy-default-porting-layer.h is not going to be included.
......@@ -140,7 +140,7 @@ Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h)
The easiest way to prepare the PHY porting layer for custom board is to copy
existing example to a new platform:
- cp ``plat/marvell/a8k/a80x0/board/phy-porting-layer.h`` "plat/marvell/<soc family>/<platform>/board/phy-porting-layer.h"
- cp ``plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h`` "plat/marvell/armada/<soc family>/<platform>/board/phy-porting-layer.h"
- adjust relevant parameters or
- if different comphy index is used for specific feature, move it to proper table entry and then adjust.
......@@ -150,7 +150,7 @@ Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h)
- Example:
Example porting layer for armada-8040-db is under:
``plat/marvell/a8k/a80x0/board/phy-porting-layer.h``
``plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h``
.. note::
If there is no PHY porting layer for new platform (missing
......
......@@ -5,10 +5,10 @@ Marvell
:maxdepth: 1
:caption: Contents
build
porting
misc/mvebu-a8k-addr-map
misc/mvebu-amb
misc/mvebu-ccu
misc/mvebu-io-win
misc/mvebu-iob
armada/build
armada/porting
armada/misc/mvebu-a8k-addr-map
armada/misc/mvebu-amb
armada/misc/mvebu-ccu
armada/misc/mvebu-io-win
armada/misc/mvebu-iob
......@@ -2236,7 +2236,7 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
printf("########################################################\n");
printf("# To use trained values update the ATF sources:\n");
printf("# plat/marvell/a8k/<board_type>/board/phy-porting-layer.h ");
printf("# plat/marvell/armada/a8k/<board_type>/board/phy-porting-layer.h ");
printf("file\n# with new values as below (for appropriate AP nr %d",
ap_nr);
printf("and CP nr: %d comphy_index %d\n\n",
......
......@@ -7,7 +7,7 @@
/* Those are parameters for xfi mode, which need to be tune for each board type.
* For known DB boards the parameters was already calibrated and placed under
* the plat/marvell/a8k/<board_type>/board/phy-porting-layer.h
* the plat/marvell/armada/a8k/<board_type>/board/phy-porting-layer.h
*/
struct xfi_params {
uint8_t g1_ffe_res_sel;
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment