Commit b3ce966a authored by Mounika Grace Akula's avatar Mounika Grace Akula Committed by Jolly Shah
Browse files

zynqmp: pm: Add LPD WDT clock to the pm_clock structure



This patch adds LPD WDT clock node to the pm_clock clocks structure list
so that LPD WDT can be used from Linux.

Also this patch removes the CLK_LPD_LSBUS from invalid clock list to
allow the registration of this clock to CCF framework as it is the
parent of LPD WDT.

Signed-off-by: default avatarMounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: default avatarJolly Shah <jolly.shah@xilinx.com>
Change-Id: Iea065aa8150eaba4bb4b42bc6be1fd4b7fe7b403
parent 06ad9803
/*
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -330,6 +330,7 @@
#define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308)
#define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304)
#define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100)
#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300)
/* Global general storage register base address */
#define GGS_BASEADDR (0xFFD80030U)
......
......@@ -2198,6 +2198,18 @@ static struct pm_clock clocks[] = {
.nodes = &can1_nodes,
.num_nodes = ARRAY_SIZE(can1_nodes),
},
[CLK_LPD_WDT] = {
.name = "lpd_wdt",
.control_reg = IOU_SLCR_WDT_CLK_SEL,
.status_reg = 0,
.parents = &((int32_t []) {
CLK_LPD_LSBUS,
EXT_CLK_SWDT1 | CLK_EXTERNAL_PARENT,
CLK_NA_PARENT
}),
.nodes = &wdt_nodes,
.num_nodes = ARRAY_SIZE(wdt_nodes),
},
};
static struct pm_ext_clock ext_clocks[] = {
......@@ -2343,7 +2355,6 @@ static uint32_t pm_clk_invalid_list[] = {CLK_USB0, CLK_USB1, CLK_CSU_SPB,
CLK_TOPSW_LSBUS,
CLK_GTGREF0_REF,
CLK_LPD_SWITCH,
CLK_LPD_LSBUS,
CLK_CPU_R5,
CLK_CPU_R5_CORE,
CLK_CSU_SPB,
......
......@@ -169,6 +169,7 @@ enum clock_id {
CLK_GEM1_REF_UNGATED,
CLK_GEM2_REF_UNGATED,
CLK_GEM3_REF_UNGATED,
CLK_LPD_WDT,
END_OF_OUTPUT_CLKS,
};
......
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