1. 08 Dec, 2020 3 commits
    • Ravi Patel's avatar
      zynqmp: pm: Update flags in common clk divisor node · c8f62536
      Ravi Patel authored
      Current implementation doesn't support change of div1 value if clk
      has 2 divisor because div1 clk is the parent of the div2 clk and div2
      clk does not have SET_RATE_PARENT flag.
      This causes div1 value to be fixed and only value of div2 will be
      adjusted according to required clock rate.
       Consider a case of nand_ref clock which has 2 divisor and 1 mux.
       The frequency of mux clock is 1500MHz and default value of div1 and
       div2 is 15 and 1 respectively. So the final clock will be of 100MHz.
       When driver requests 80MHz for nand_ref clock, clock framework will
       adjust the div2 value to 1 (setting div2 value 2 results final clock
       to 50MHz which is more inaccurate compare to 100Mhz) which results
       final clock to 100MHz.
       Ideally the value of div1 and div2 should be updated to 19 and 1
       respectively so that final clock goes to around 78MHz.
      This patch fixes above problem by allowing change in div1 value.
      Signed-off-by: default avatarRavi Patel <ravi.patel@xilinx.com>
      Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
      Change-Id: Ibb98f6748d28653fdd1e59bf433b6a37ce9c1a58
    • Siva Durga Prasad Paladugu's avatar
      zynqmp: pm_api_clock: Copy only the valid bytes · f2afaad0
      Siva Durga Prasad Paladugu authored
      This patches copies only the valid part of string and
      avoids filling junk at the end.
      Signed-off-by: default avatarSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
      Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
      Change-Id: If23772f31f9cf7f5042e8bfc474fbfe77dcd90e7
    • Manish Pandey's avatar
      Merge changes Ibbee37c8,Ic3a13c83,Ib7f2380a,I83b477fd,I284956d4, ... into integration · 77990838
      Manish Pandey authored
      * changes:
        mediatek: mt8192: dcm: Add mcusys related dcm drivers
        mediatek: mt8192: add ptp3 driver
        mediatek: mt8192: Add SiP service
        mediatek: mt8192: add uart save and restore api
        mediatek: mt8192: modify sys_cirq driver
        mediatek: mt8192: add power-off support
        mediatek: mt8192: add pmic mt6359p driver
        mediatek: mt8192: Initialize delay_timer
        mediatek: mt8192: enable NS access for systimer
        mediatek: mt8192: Add CPU hotplug and MCDI support
        mediatek: mt8192: Add MCDI drivers
        mediatek: mt8192: Add SPMC driver
  2. 07 Dec, 2020 26 commits
  3. 05 Dec, 2020 1 commit
  4. 04 Dec, 2020 1 commit
  5. 03 Dec, 2020 6 commits
  6. 02 Dec, 2020 3 commits