Verified Commit 9c51cc75 authored by Vincent Coubard's avatar Vincent Coubard
Browse files

Update Corstone-310 target to match keyword requirements



- Adjust memory regions
- Set peripheral and memory config
Signed-off-by: Vincent Coubard's avatarVincent Coubard <vincent.coubard@arm.com>
parent 1a5bbf86
......@@ -48,7 +48,17 @@ if(NS)
)
target_link_libraries(CMSIS_5_tfm_ns
INTERFACE
CMSIS_5_RTX_V8MMN
$<$<STREQUAL:${CONFIG_TFM_FP},hard>:CMSIS_5_RTX_V8MMFN>
$<$<STREQUAL:${CONFIG_TFM_FP},soft>:CMSIS_5_RTX_V8MMN>
)
target_compile_options(tfm_ns
PUBLIC
${COMPILER_CP_FLAG}
)
target_link_options(tfm_ns
PUBLIC
${LINKER_CP_OPTION}
)
endif()
......@@ -148,6 +158,11 @@ target_include_directories(platform_ns
partition
)
target_link_libraries(platform_ns
PRIVATE
psa_interface
)
#========================= Platform BL2 =======================================#
if(BL2)
......
......@@ -26,9 +26,9 @@
#define ARG_UNUSED(arg) ((void)arg)
#endif
#define FLASH0_BASE_S SRAM_BASE_S
#define FLASH0_BASE_NS SRAM_BASE_NS
#define FLASH0_SIZE SRAM_SIZE
#define FLASH0_BASE_S QSPI_SRAM_BASE_S
#define FLASH0_BASE_NS QSPI_SRAM_BASE_NS
#define FLASH0_SIZE QSPI_SRAM_SIZE
#define FLASH0_SECTOR_SIZE 0x00001000 /* 4 kB */
#define FLASH0_PAGE_SIZE 0x00001000 /* 4 kB */
#define FLASH0_PROGRAM_UNIT 0x1 /* Minimum write size */
......
/*
* Copyright (c) 2016-2020 Arm Limited. All rights reserved.
* Copyright (c) 2016-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
......@@ -624,26 +624,73 @@ ARM_DRIVER_MPC Driver_QSPI_MPC = {
#endif /* RTE_QSPI_MPC */
#if (RTE_DDR4_MPC)
/* Ranges controlled by this DDR4_MPC */
static const struct mpc_sie_memory_range_t MPC_DDR4_RANGE_S = {
.base = MPC_DDR4_RANGE_BASE_S,
.limit = MPC_DDR4_RANGE_LIMIT_S,
.range_offset = 0,
#define MPC_DDR4_RANGE_LIST_LEN 8u
static const struct mpc_sie_memory_range_t MPC_DDR4_BLK0_RANGE_NS = {
.base = MPC_DDR4_BLK0_RANGE_BASE_NS,
.limit = MPC_DDR4_BLK0_RANGE_LIMIT_NS,
.range_offset = MPC_DDR4_BLK0_RANGE_OFFSET_NS,
.attr = MPC_SIE_SEC_ATTR_NONSECURE
};
static const struct mpc_sie_memory_range_t MPC_DDR4_BLK1_RANGE_S = {
.base = MPC_DDR4_BLK1_RANGE_BASE_S,
.limit = MPC_DDR4_BLK1_RANGE_LIMIT_S,
.range_offset = MPC_DDR4_BLK1_RANGE_OFFSET_S,
.attr = MPC_SIE_SEC_ATTR_SECURE
};
static const struct mpc_sie_memory_range_t MPC_DDR4_RANGE_NS = {
.base = MPC_DDR4_RANGE_BASE_NS,
.limit = MPC_DDR4_RANGE_LIMIT_NS,
.range_offset = 0,
static const struct mpc_sie_memory_range_t MPC_DDR4_BLK2_RANGE_NS = {
.base = MPC_DDR4_BLK2_RANGE_BASE_NS,
.limit = MPC_DDR4_BLK2_RANGE_LIMIT_NS,
.range_offset = MPC_DDR4_BLK2_RANGE_OFFSET_NS,
.attr = MPC_SIE_SEC_ATTR_NONSECURE
};
static const struct mpc_sie_memory_range_t MPC_DDR4_BLK3_RANGE_S = {
.base = MPC_DDR4_BLK3_RANGE_BASE_S,
.limit = MPC_DDR4_BLK3_RANGE_LIMIT_S,
.range_offset = MPC_DDR4_BLK3_RANGE_OFFSET_S,
.attr = MPC_SIE_SEC_ATTR_SECURE
};
static const struct mpc_sie_memory_range_t MPC_DDR4_BLK4_RANGE_NS = {
.base = MPC_DDR4_BLK4_RANGE_BASE_NS,
.limit = MPC_DDR4_BLK4_RANGE_LIMIT_NS,
.range_offset = MPC_DDR4_BLK4_RANGE_OFFSET_NS,
.attr = MPC_SIE_SEC_ATTR_NONSECURE
};
static const struct mpc_sie_memory_range_t MPC_DDR4_BLK5_RANGE_S = {
.base = MPC_DDR4_BLK5_RANGE_BASE_S,
.limit = MPC_DDR4_BLK5_RANGE_LIMIT_S,
.range_offset = MPC_DDR4_BLK5_RANGE_OFFSET_S,
.attr = MPC_SIE_SEC_ATTR_SECURE
};
static const struct mpc_sie_memory_range_t MPC_DDR4_BLK6_RANGE_NS = {
.base = MPC_DDR4_BLK6_RANGE_BASE_NS,
.limit = MPC_DDR4_BLK6_RANGE_LIMIT_NS,
.range_offset = MPC_DDR4_BLK6_RANGE_OFFSET_NS,
.attr = MPC_SIE_SEC_ATTR_NONSECURE
};
#define MPC_DDR4_RANGE_LIST_LEN 2u
static const struct mpc_sie_memory_range_t MPC_DDR4_BLK7_RANGE_S = {
.base = MPC_DDR4_BLK7_RANGE_BASE_S,
.limit = MPC_DDR4_BLK7_RANGE_LIMIT_S,
.range_offset = MPC_DDR4_BLK7_RANGE_OFFSET_S,
.attr = MPC_SIE_SEC_ATTR_SECURE
};
static const struct mpc_sie_memory_range_t*
MPC_DDR4_RANGE_LIST[MPC_DDR4_RANGE_LIST_LEN] = {
&MPC_DDR4_RANGE_S,
&MPC_DDR4_RANGE_NS
&MPC_DDR4_BLK0_RANGE_NS,
&MPC_DDR4_BLK1_RANGE_S,
&MPC_DDR4_BLK2_RANGE_NS,
&MPC_DDR4_BLK3_RANGE_S,
&MPC_DDR4_BLK4_RANGE_NS,
&MPC_DDR4_BLK5_RANGE_S,
&MPC_DDR4_BLK6_RANGE_NS,
&MPC_DDR4_BLK7_RANGE_S,
};
/* DDR4_MPC Driver wrapper functions */
......
/*
* Copyright (c) 2019-2021 Arm Limited. All rights reserved.
* Copyright (c) 2019-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
......@@ -43,6 +43,10 @@
// <i> Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC
#define RTE_QSPI_MPC 1
// <e> MPC (Memory Protection Controller) [Driver_DDR4_MPC]
// <i> Configuration settings for Driver_DDR4_MPC in component ::Drivers:MPC
#define RTE_DDR4_MPC 1
// <q> PPC (Peripheral Protection Controller) [PPC_POLARIS_MAIN0]
// <i> Configuration settings for Driver_PPC_POLARIS_MAIN0 in component ::Drivers:PPC
#define RTE_PPC_POLARIS_MAIN0 1
......
/*
* Copyright (c) 2019-2021 Arm Limited. All rights reserved.
* Copyright (c) 2019-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
......@@ -29,6 +29,9 @@
#define MPC_ISRAM1_S
#define MPC_SRAM_S
#define MPC_QSPI_S
#define MPC_DDR4_S
#define MPC_DDR4_DEV MPC_DDR4_DEV_S
/* ARM Peripheral Protection Controllers (PPC) */
#define PPC_POLARIS_MAIN0_S
......@@ -62,7 +65,9 @@
/* System Timer Armv8-M */
#define SYSTIMER0_ARMV8_M_S
#define SYSTIMER1_ARMV8_M_NS
#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul)
#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
#endif /* __DEVICE_CFG_H__ */
/*
* Copyright (c) 2019-2021 Arm Limited
* Copyright (c) 2019-2022 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
......@@ -326,6 +326,7 @@ struct polaris_nsacfg_t {
#define UART5_PERIPH_PPCEXP2_POS_MASK (1UL << 8)
#define CLCD_PERIPH_PPCEXP2_POS_MASK (1UL << 10)
#define RTC_PERIPH_PPCEXP2_POS_MASK (1UL << 11)
#define VSI_PERIPH_PPCEXP2_POS_MASK (1UL << 12)
/* End PERIPH PPCEXP2 peripherals definition */
/* PERIPH PPCEXP3 peripherals definition */
......
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
* Copyright (c) 2009-2022 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
......@@ -170,6 +170,8 @@ DEFAULT_IRQ_HANDLER(GPIO3_3_Handler)
DEFAULT_IRQ_HANDLER(UARTRX5_Handler)
DEFAULT_IRQ_HANDLER(UARTTX5_Handler)
DEFAULT_IRQ_HANDLER(UART5_Handler)
DEFAULT_IRQ_HANDLER(ARM_VSI0_Handler)
DEFAULT_IRQ_HANDLER(arm_npu_irq_handler)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
......@@ -215,7 +217,7 @@ extern const pFunc __VECTOR_TABLE[];
0, /* 13: Reserved */
COMBINED_PPU_Handler, /* 14: Combined PPU Handler */
0, /* 15: Reserved */
ETHOS_U55_Handler, /* 16: Ethos-U55 Handler */
arm_npu_irq_handler, /* 16: Ethos-U55 Handler */
0, /* 17: Reserved */
0, /* 18: Reserved */
0, /* 19: Reserved */
......@@ -332,6 +334,100 @@ extern const pFunc __VECTOR_TABLE[];
0, /* 128: Reserved */
0, /* 129: Reserved */
0, /* 130: Reserved */
0, /* 131: Reserved */
0, /* 132: Reserved */
0, /* 133: Reserved */
0, /* 134: Reserved */
0, /* 135: Reserved */
0, /* 136: Reserved */
0, /* 137: Reserved */
0, /* 138: Reserved */
0, /* 139: Reserved */
0, /* 140: Reserved */
0, /* 141: Reserved */
0, /* 142: Reserved */
0, /* 143: Reserved */
0, /* 144: Reserved */
0, /* 145: Reserved */
0, /* 146: Reserved */
0, /* 147: Reserved */
0, /* 148: Reserved */
0, /* 149: Reserved */
0, /* 150: Reserved */
0, /* 151: Reserved */
0, /* 152: Reserved */
0, /* 153: Reserved */
0, /* 154: Reserved */
0, /* 155: Reserved */
0, /* 156: Reserved */
0, /* 157: Reserved */
0, /* 158: Reserved */
0, /* 159: Reserved */
0, /* 160: Reserved */
0, /* 161: Reserved */
0, /* 162: Reserved */
0, /* 163: Reserved */
0, /* 164: Reserved */
0, /* 165: Reserved */
0, /* 166: Reserved */
0, /* 167: Reserved */
0, /* 168: Reserved */
0, /* 169: Reserved */
0, /* 170: Reserved */
0, /* 171: Reserved */
0, /* 172: Reserved */
0, /* 173: Reserved */
0, /* 174: Reserved */
0, /* 175: Reserved */
0, /* 176: Reserved */
0, /* 177: Reserved */
0, /* 178: Reserved */
0, /* 179: Reserved */
0, /* 180: Reserved */
0, /* 181: Reserved */
0, /* 182: Reserved */
0, /* 183: Reserved */
0, /* 184: Reserved */
0, /* 185: Reserved */
0, /* 186: Reserved */
0, /* 187: Reserved */
0, /* 188: Reserved */
0, /* 189: Reserved */
0, /* 190: Reserved */
0, /* 191: Reserved */
0, /* 192: Reserved */
0, /* 193: Reserved */
0, /* 194: Reserved */
0, /* 195: Reserved */
0, /* 196: Reserved */
0, /* 197: Reserved */
0, /* 198: Reserved */
0, /* 199: Reserved */
0, /* 200: Reserved */
0, /* 201: Reserved */
0, /* 202: Reserved */
0, /* 203: Reserved */
0, /* 204: Reserved */
0, /* 205: Reserved */
0, /* 206: Reserved */
0, /* 207: Reserved */
0, /* 208: Reserved */
0, /* 209: Reserved */
0, /* 210: Reserved */
0, /* 211: Reserved */
0, /* 212: Reserved */
0, /* 213: Reserved */
0, /* 214: Reserved */
0, /* 215: Reserved */
0, /* 216: Reserved */
0, /* 217: Reserved */
0, /* 218: Reserved */
0, /* 219: Reserved */
0, /* 220: Reserved */
0, /* 221: Reserved */
0, /* 222: Reserved */
0, /* 223: Reserved */
ARM_VSI0_Handler, /* 224: VSI 0 */
};
#if defined ( __GNUC__ )
......
/*
* Copyright (c) 2019-2021 Arm Limited. All rights reserved.
* Copyright (c) 2019-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
......@@ -19,32 +19,32 @@
#include "platform_base_address.h"
/* WARNING: Layout below has been moved to QSPI_SRAM and addresses were changed */
/* Flash layout on Corstone-Polaris with BL2 (multiple image boot):
*
* 0x0000_0000 Secure image primary slot (384 KB)
* 0x0006_0000 Non-secure image primary slot (384 KB)
* 0x000C_0000 Secure image secondary slot (384 KB)
* 0x0012_0000 Non-secure image secondary slot (384 KB)
* 0x0018_0000 Scratch area (384 KB)
* 0x001E_0000 Protected Storage Area (20 KB)
* 0x001E_5000 Internal Trusted Storage Area (16 KB)
* 0x001E_9000 OTP / NV counters area (8 KB)
* 0x001E_B000 Unused
* 0x0006_0000 Non-secure image primary slot (2 MB)
* 0x0206_0000 Secure image secondary slot (384 KB)
* 0x020C_0000 Non-secure image secondary slot (2 MB)
* 0x040C_0000 Scratch area (2 MB)
* 0x060C_0000 Protected Storage Area (20 KB)
* 0x060C_5000 Internal Trusted Storage Area (16 KB)
* 0x060C_9000 OTP / NV counters area (8 KB)
* 0x060C_B000 Unused
*
* Flash layout on Corstone-Polaris with BL2 (single image boot):
*
* 0x0000_0000 Primary image area (768 KB):
* 0x0000_0000 Secure image primary (384 KB)
* 0x0006_0000 Non-secure image primary (384 KB)
* 0x000C_0000 Secondary image area (768 KB):
* 0x000C_0000 Secure image secondary (384 KB)
* 0x0012_0000 Non-secure image secondary (384 KB)
* 0x0018_0000 Scratch area (384 KB)
* 0x001C_0000 Protected Storage Area (20 KB)
* 0x001C_5000 Internal Trusted Storage Area (16 KB)
* 0x001C_9000 NV counters area (4 KB)
* 0x001E_9000 OTP / NV counters area (8 KB)
* 0x001E_B000 Unused
* 0x0206_0000 Secondary image area (768 KB):
* 0x0206_0000 Secure image secondary (384 KB)
* 0x020C_0000 Non-secure image secondary (384 KB)
* 0x040C_0000 Scratch area (2 MB)
* 0x060C_0000 Protected Storage Area (20 KB)
* 0x060C_5000 Internal Trusted Storage Area (16 KB)
* 0x060C_9000 OTP / NV counters area (8 KB)
* 0x060C_B000 Unused
*/
......@@ -58,7 +58,7 @@
/* Size of a Secure and of a Non-secure image */
#define FLASH_S_PARTITION_SIZE (0x60000) /* S partition: 384 KB */
#define FLASH_NS_PARTITION_SIZE (0x60000) /* NS partition: 384 KB */
#define FLASH_NS_PARTITION_SIZE (0x200000) /* NS partition: 2MB */
#define FLASH_MAX_PARTITION_SIZE ((FLASH_S_PARTITION_SIZE > \
FLASH_NS_PARTITION_SIZE) ? \
FLASH_S_PARTITION_SIZE : \
......@@ -67,11 +67,11 @@
/* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */
#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB */
/* Same as FLASH0_SIZE */
#define FLASH_TOTAL_SIZE (SRAM_SIZE) /* 2 MB */
#define FLASH_TOTAL_SIZE (QSPI_SRAM_SIZE) /* 8 MB */
/* Flash layout info for BL2 bootloader */
/* Same as FLASH0_BASE_S */
#define FLASH_BASE_ADDRESS (SRAM_BASE_S)
#define FLASH_BASE_ADDRESS (QSPI_SRAM_BASE_S)
/* Offset and size definitions of the flash partitions that are handled by the
* bootloader. The image swapping is done between IMAGE_PRIMARY and
......@@ -84,7 +84,7 @@
#if !defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1)
/* Secure + Non-secure image primary slot */
#define FLASH_AREA_0_ID (1)
#define FLASH_AREA_0_OFFSET (0)
#define FLASH_AREA_0_OFFSET (0)//(FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE)//
#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE + \
FLASH_NS_PARTITION_SIZE)
/* Secure + Non-secure secondary slot */
......@@ -107,7 +107,7 @@
#elif (MCUBOOT_IMAGE_NUMBER == 2)
/* Secure image primary slot */
#define FLASH_AREA_0_ID (1)
#define FLASH_AREA_0_OFFSET (0)
#define FLASH_AREA_0_OFFSET (0)//(FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE)//
#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE)
/* Non-secure image primary slot */
#define FLASH_AREA_1_ID (FLASH_AREA_0_ID + 1)
......@@ -137,7 +137,7 @@
/* mpc_init_cfg function in target_cfg.c expects that all the images can fit
* in SRAM area. */
#if ( FLASH_AREA_SCRATCH_OFFSET + FLASH_AREA_SCRATCH_SIZE > SRAM_SIZE)
#if ( FLASH_AREA_SCRATCH_OFFSET + FLASH_AREA_SCRATCH_SIZE > QSPI_SRAM_SIZE)
#error "Out of SRAM memory!"
#endif
......
/*
* Copyright (c) 2019-2021 Arm Limited. All rights reserved.
* Copyright (c) 2019-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
......@@ -28,9 +28,9 @@
#define S_MSP_STACK_SIZE (0x0000800)
#define S_PSP_STACK_SIZE (0x0000800)
#define NS_HEAP_SIZE (0x0001000)
#define NS_MSP_STACK_SIZE (0x0000400)
#define NS_PSP_STACK_SIZE (0x0000C00)
#define NS_HEAP_SIZE (0x0008000)
#define NS_MSP_STACK_SIZE (0x0000800)
#define NS_PSP_STACK_SIZE (0x0002000)
/* This size of buffer is big enough to store an attestation
* token produced by initial attestation service
......@@ -83,12 +83,14 @@
#define IMAGE_NS_CODE_SIZE \
(FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
#define CMSE_VENEER_REGION_SIZE (0x340)
/* Secure regions */
#define S_IMAGE_PRIMARY_AREA_OFFSET \
(S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
/* Secure Code stored in Code SRAM */
#define S_CODE_START ((SRAM_BASE_S) + (S_IMAGE_PRIMARY_AREA_OFFSET))
#define S_CODE_SIZE (IMAGE_S_CODE_SIZE)
#define S_CODE_START ((QSPI_SRAM_BASE_S) + (S_IMAGE_PRIMARY_AREA_OFFSET))
#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
/* Secure Data stored in DTCM */
......@@ -103,23 +105,23 @@
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
(NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
/* Non-Secure Code stored in Code SRAM memory */
#define NS_CODE_START (SRAM_BASE_NS + (NS_IMAGE_PRIMARY_AREA_OFFSET))
#define NS_CODE_START (QSPI_SRAM_BASE_NS + (NS_IMAGE_PRIMARY_AREA_OFFSET))
#define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE)
#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1)
/* Non-Secure Data stored in ISRAM0 */
#define NS_DATA_START (ISRAM0_BASE_NS)
#define NS_DATA_SIZE (ISRAM0_SIZE)
#define NS_DATA_SIZE (ISRAM0_SIZE + ISRAM1_SIZE)
#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1)
/* NS partition information is used for MPC and SAU configuration */
#define NS_PARTITION_START \
((SRAM_BASE_NS) + (NS_IMAGE_PRIMARY_PARTITION_OFFSET))
((QSPI_SRAM_BASE_NS) + (NS_IMAGE_PRIMARY_PARTITION_OFFSET))
#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE)
/* Secondary partition for new images in case of firmware upgrade */
#define SECONDARY_PARTITION_START \
((SRAM_BASE_NS) + (S_IMAGE_SECONDARY_PARTITION_OFFSET))
((QSPI_SRAM_BASE_NS) + (S_IMAGE_SECONDARY_PARTITION_OFFSET))
#define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + \
FLASH_NS_PARTITION_SIZE)
......
/*
* Copyright (c) 2019-2021 Arm Limited. All rights reserved.
* Copyright (c) 2019-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
......@@ -33,6 +33,9 @@
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
REGION_DECLARE(Image$$, ER_VENEER, $$Base);
REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
#ifdef BL2
REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
#endif /* BL2 */
const struct memory_region_limits memory_regions = {
.non_secure_code_start =
......@@ -48,6 +51,15 @@ const struct memory_region_limits memory_regions = {
.veneer_base = (uint32_t)&REGION_NAME(Image$$, ER_VENEER, $$Base),
.veneer_limit = (uint32_t)&REGION_NAME(Image$$, VENEER_ALIGN, $$Limit),
#ifdef BL2
.secondary_partition_base =
(uint32_t)&REGION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base),
.secondary_partition_limit =
(uint32_t)&REGION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base) +
SECONDARY_PARTITION_SIZE - 1,
#endif /* BL2 */
};
/* Configures the RAM region to NS callable in sacfg block's nsccfg register */
......@@ -60,6 +72,7 @@ extern ARM_DRIVER_MPC Driver_ISRAM0_MPC;
extern ARM_DRIVER_MPC Driver_ISRAM1_MPC;
extern ARM_DRIVER_MPC Driver_SRAM_MPC;
extern ARM_DRIVER_MPC Driver_QSPI_MPC;
extern ARM_DRIVER_MPC Driver_DDR4_MPC;
/* Import PPC drivers */
extern DRIVER_PPC_POLARIS Driver_PPC_POLARIS_MAIN0;
......@@ -200,6 +213,17 @@ enum tfm_plat_err_t nvic_interrupt_enable(void)
ERROR_MSG("Failed to Enable MPC interrupt for ISRAM0!");
return TFM_PLAT_ERR_SYSTEM_ERR;
}
ret = Driver_ISRAM1_MPC.EnableInterrupt();
if (ret != ARM_DRIVER_OK) {
ERROR_MSG("Failed to Enable MPC interrupt for ISRAM1!");
return TFM_PLAT_ERR_SYSTEM_ERR;
}
ret = Driver_DDR4_MPC.EnableInterrupt();
if (ret != ARM_DRIVER_OK) {
ERROR_MSG("Failed to Enable MPC interrupt for DDR4!");
return TFM_PLAT_ERR_SYSTEM_ERR;
}
ret = Driver_SRAM_MPC.EnableInterrupt();
if (ret != ARM_DRIVER_OK) {
......@@ -207,6 +231,12 @@ enum tfm_plat_err_t nvic_interrupt_enable(void)
return TFM_PLAT_ERR_SYSTEM_ERR;
}
ret = Driver_QSPI_MPC.EnableInterrupt();
if (ret != ARM_DRIVER_OK) {
ERROR_MSG("Failed to Enable MPC interrupt for QSPI!");
return TFM_PLAT_ERR_SYSTEM_ERR;
}
NVIC_ClearPendingIRQ(MPC_IRQn);
NVIC_EnableIRQ(MPC_IRQn);
......@@ -272,22 +302,23 @@ enum tfm_plat_err_t init_debug(void)
/*------------------- SAU/IDAU configuration functions -----------------------*/
void sau_and_idau_cfg(void)
{
struct polaris_sacfg_t *sacfg = (struct polaris_sacfg_t*)POLARIS_SACFG_BASE_S;
struct polaris_sacfg_t *sacfg = (struct sse300_sacfg_t*)POLARIS_SACFG_BASE_S;
/* Enables SAU */
TZ_SAU_Enable();
/* Configures SAU regions to be non-secure */
SAU->RNR = 0;
SAU->RBAR = (ISRAM0_BASE_NS & SAU_RBAR_BADDR_Msk);
SAU->RLAR = ((ISRAM0_BASE_NS + ISRAM0_SIZE + ISRAM1_SIZE - 1) & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
/* Configures SAU regions to be non-secure */
SAU->RNR = 1;
SAU->RBAR = (memory_regions.non_secure_partition_base
& SAU_RBAR_BADDR_Msk);
SAU->RLAR = (memory_regions.non_secure_partition_limit
& SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
SAU->RNR = 1;
SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk);
SAU->RLAR = (NS_DATA_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
/* Configures veneers region to be non-secure callable */
SAU->RNR = 2;
SAU->RBAR = (memory_regions.veneer_base & SAU_RBAR_BADDR_Msk);
......@@ -300,8 +331,33 @@ void sau_and_idau_cfg(void)
SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk)
| SAU_RLAR_ENABLE_Msk;
/* Secondary image partition */
SAU->RNR = 4;
SAU->RBAR = (memory_regions.secondary_partition_base
& SAU_RBAR_BADDR_Msk);