Import corstone Polaris target from TF-M

Signed-off-by: Vincent Coubard <vincent.coubard@arm.com>

bsp/tf_m_targets/arm/mps3/corstone_polaris/CMakeLists.txt

+#-------------------------------------------------------------------------------
+# Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+cmake_policy(SET CMP0076 NEW)
+set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR})
+
+#========================= Platform region defs ===============================#
+
+target_include_directories(platform_region_defs
+    INTERFACE
+        partition
+)
+
+#========================= Platform common defs ===============================#
+
+if (${CMAKE_C_COMPILER_ID} STREQUAL IAR)
+    message(FATAL_ERROR "IAR is currently not supported on the mps3/corstone_polaris due to a lack of scatter files")
+endif()
+
+if (${CMAKE_C_COMPILER_ID} STREQUAL ARMClang)
+    if (${CMAKE_C_COMPILER_VERSION} VERSION_LESS "6.14")
+        message(FATAL_ERROR "Architecture (Armv8.1-M) is only supported in ARMCLANG version 6.14 or newer.")
+    endif()
+endif()
+
+# Specify the location of platform specific build dependencies.
+target_sources(tfm_s
+    PRIVATE
+    ${CMAKE_CURRENT_SOURCE_DIR}/device/source/startup_corstone_polaris_s.c
+)
+target_add_scatter_file(tfm_s
+    $<$<C_COMPILER_ID:ARMClang>:${CMAKE_SOURCE_DIR}/platform/ext/common/armclang/tfm_common_s.sct>
+    $<$<C_COMPILER_ID:GNU>:${CMAKE_SOURCE_DIR}/platform/ext/common/gcc/tfm_common_s.ld>
+)
+
+if(NS)
+    target_sources(tfm_ns
+        PRIVATE
+            ${CMAKE_CURRENT_SOURCE_DIR}/device/source/startup_corstone_polaris_ns.c
+    )
+    target_add_scatter_file(tfm_ns
+        $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/armclang/corstone_polaris_ns.sct>
+        $<$<C_COMPILER_ID:GNU>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/gcc/corstone_polaris_ns.ld>
+    )
+    target_link_libraries(CMSIS_5_tfm_ns
+        INTERFACE
+            CMSIS_5_RTX_V8MMN
+    )
+endif()
+
+if(BL2)
+    target_sources(bl2
+        PRIVATE
+            ${CMAKE_CURRENT_SOURCE_DIR}/device/source/startup_corstone_polaris_bl2.c
+    )
+    target_add_scatter_file(bl2
+            $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/armclang/corstone_polaris_bl2.sct>
+            $<$<C_COMPILER_ID:GNU>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/gcc/corstone_polaris_bl2.ld>
+    )
+endif()
+
+#========================= Platform Secure ====================================#
+
+target_include_directories(platform_s
+    PUBLIC
+        .
+        ../common
+        cmsis_drivers
+        cmsis_drivers/config
+        device
+        device/config
+        device/include
+        device/source/armclang
+        native_drivers
+        partition
+        services/src
+        ${PLATFORM_DIR}/..
+)
+
+target_sources(platform_s
+    PRIVATE
+        cmsis_drivers/Driver_Flash.c
+        cmsis_drivers/Driver_MPC.c
+        cmsis_drivers/Driver_PPC.c
+        cmsis_drivers/Driver_USART.c
+        device/source/device_definition.c
+        device/source/system_core_init.c
+        native_drivers/mpc_sie_drv.c
+        native_drivers/mpu_armv8m_drv.c
+        native_drivers/ppc_polaris_drv.c
+        native_drivers/syscounter_armv8-m_cntrl_drv.c
+        native_drivers/uart_cmsdk_drv.c
+        spm_hal.c
+        $<$<BOOL:${TFM_PSA_API}>:${CMAKE_CURRENT_SOURCE_DIR}/tfm_interrupts.c>
+        target_cfg.c
+        tfm_hal_isolation.c
+        tfm_hal_platform.c
+        ${CMAKE_SOURCE_DIR}/platform/ext/common/tfm_hal_nvic.c
+        ${CMAKE_SOURCE_DIR}/platform/ext/common/tfm_hal_isolation_mpu_v8m.c
+        $<$<OR:$<BOOL:${TEST_NS_SLIH_IRQ}>,$<BOOL:${TEST_NS_FLIH_IRQ}>>:${CMAKE_CURRENT_SOURCE_DIR}/plat_test.c>
+        $<$<BOOL:${TFM_PARTITION_PLATFORM}>:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c>
+)
+
+target_sources(tfm_sprt
+    PRIVATE
+        # SLIH test Partition and FLIH test Partition access the timer as ARoT Partitions.
+        # Put the driver to SPRT so that both SLIH and FLIH tests can access it.
+        $<$<OR:$<BOOL:${TEST_NS_SLIH_IRQ}>,$<BOOL:${TEST_NS_FLIH_IRQ}>>:${CMAKE_CURRENT_SOURCE_DIR}/native_drivers/systimer_armv8-m_drv.c>
+)
+
+target_link_libraries(platform_s
+    PRIVATE
+        tfm_utilities
+)
+
+target_compile_options(platform_s
+    PUBLIC
+        ${COMPILER_CMSE_FLAG}
+)
+
+#========================= Platform Non-Secure ================================#
+
+target_sources(platform_ns
+    PRIVATE
+        cmsis_drivers/Driver_Flash.c
+        cmsis_drivers/Driver_USART.c
+        device/source/device_definition.c
+        device/source/system_core_init.c
+        native_drivers/uart_cmsdk_drv.c
+)
+
+target_include_directories(platform_ns
+    PUBLIC
+        .
+        ../common
+        ${PLATFORM_DIR}/..
+        cmsis_drivers
+        cmsis_drivers/config
+        device
+        device/config
+        device/include
+        device/source/armclang
+        native_drivers
+        partition
+)
+
+#========================= Platform BL2 =======================================#
+
+if(BL2)
+    target_sources(platform_bl2
+        PRIVATE
+            cmsis_drivers/Driver_Flash.c
+            cmsis_drivers/Driver_USART.c
+            device/source/device_definition.c
+            device/source/system_core_init.c
+            native_drivers/uart_cmsdk_drv.c
+    )
+
+    target_include_directories(platform_bl2
+        PUBLIC
+            cmsis_drivers
+            cmsis_drivers/config
+            device
+            device/config
+            device/include
+            device/source/armclang
+            native_drivers
+            partition
+            services/src
+
+        PRIVATE
+            .
+            ${PLATFORM_DIR}/..
+            native_drivers
+    )
+endif()

bsp/tf_m_targets/arm/mps3/corstone_polaris/README.rst

+Corstone-Polaris
+================
+
+Introduction
+------------
+
+Corstone-Polaris is an Arm reference subsystem for secure System on
+Chips containing an Armv8.1-M Olympus processor and an Ethos-U55 neural
+network processor. It is an MPS3 based platform with the usual MPS3
+peripherals.
+
+This platform port supports all TF-M regression tests (Secure and Non-secure)
+with Isolation Level 1 and 2, but building without BL2 is not supported.
+
+Building TF-M
+-------------
+
+Follow the instructions in :doc:`Building instructions </docs/technical_references/instructions/tfm_build_instruction>`.
+Build instructions with platform name: arm/mps3/corstone_polaris (-DTFM_PLATFORM=arm/mps3/corstone_polaris).
+
+*Copyright (c) 2021, Arm Limited. All rights reserved.*

bsp/tf_m_targets/arm/mps3/corstone_polaris/cmsis_drivers/Driver_Flash.c

+/*
+ * Copyright (c) 2013-2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include "Driver_Flash.h"
+#include "RTE_Device.h"
+#include "platform_base_address.h"
+
+#ifndef ARG_UNUSED
+#define ARG_UNUSED(arg)  ((void)arg)
+#endif
+
+#define FLASH0_BASE_S         SRAM_BASE_S
+#define FLASH0_BASE_NS        SRAM_BASE_NS
+#define FLASH0_SIZE           SRAM_SIZE
+#define FLASH0_SECTOR_SIZE    0x00001000 /* 4 kB */
+#define FLASH0_PAGE_SIZE      0x00001000 /* 4 kB */
+#define FLASH0_PROGRAM_UNIT   0x1        /* Minimum write size */
+
+/* Driver version */
+#define ARM_FLASH_DRV_VERSION      ARM_DRIVER_VERSION_MAJOR_MINOR(1, 1)
+#define ARM_FLASH_DRV_ERASE_VALUE  0xFF
+
+/**
+ * Data width values for ARM_FLASH_CAPABILITIES::data_width
+ * \ref ARM_FLASH_CAPABILITIES
+ */
+ enum {
+    DATA_WIDTH_8BIT   = 0u,
+    DATA_WIDTH_16BIT,
+    DATA_WIDTH_32BIT,
+    DATA_WIDTH_ENUM_SIZE
+};
+
+static const uint32_t data_width_byte[DATA_WIDTH_ENUM_SIZE] = {
+    sizeof(uint8_t),
+    sizeof(uint16_t),
+    sizeof(uint32_t),
+};
+
+
+/*
+ * ARM FLASH device structure
+ *
+ * This driver just emulates a flash interface and behaviour on top of the SRAM
+ * memory.
+ */
+struct arm_flash_dev_t {
+    const uint32_t memory_base;   /*!< FLASH memory base address */
+    ARM_FLASH_INFO *data;         /*!< FLASH data */
+};
+
+/* Flash Status */
+static ARM_FLASH_STATUS FlashStatus = {0, 0, 0};
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_FLASH_API_VERSION,
+    ARM_FLASH_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_FLASH_CAPABILITIES DriverCapabilities = {
+    0, /* event_ready */
+    0, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */
+    1  /* erase_chip */
+};
+
+static int32_t is_range_valid(struct arm_flash_dev_t *flash_dev,
+                              uint32_t offset)
+{
+    uint32_t flash_limit = 0;
+    int32_t rc = 0;
+
+    flash_limit = (flash_dev->data->sector_count * flash_dev->data->sector_size)
+                   - 1;
+
+    if (offset > flash_limit) {
+        rc = -1;
+    }
+    return rc;
+}
+
+static int32_t is_write_aligned(struct arm_flash_dev_t *flash_dev,
+                                uint32_t param)
+{
+    int32_t rc = 0;
+
+    if ((param % flash_dev->data->program_unit) != 0) {
+        rc = -1;
+    }
+    return rc;
+}
+
+static int32_t is_sector_aligned(struct arm_flash_dev_t *flash_dev,
+                                 uint32_t offset)
+{
+    int32_t rc = 0;
+
+    if ((offset % flash_dev->data->sector_size) != 0) {
+        rc = -1;
+    }
+    return rc;
+}
+
+static int32_t is_flash_ready_to_write(const uint8_t *start_addr, uint32_t cnt)
+{
+    int32_t rc = 0;
+    uint32_t i;
+
+    for (i = 0; i < cnt; i++) {
+        if(start_addr[i] != ARM_FLASH_DRV_ERASE_VALUE) {
+            rc = -1;
+            break;
+        }
+    }
+
+    return rc;
+}
+
+#if (RTE_FLASH0)
+static ARM_FLASH_INFO ARM_FLASH0_DEV_DATA = {
+    .sector_info  = NULL,                  /* Uniform sector layout */
+    .sector_count = FLASH0_SIZE / FLASH0_SECTOR_SIZE,
+    .sector_size  = FLASH0_SECTOR_SIZE,
+    .page_size    = FLASH0_PAGE_SIZE,
+    .program_unit = FLASH0_PROGRAM_UNIT,
+    .erased_value = ARM_FLASH_DRV_ERASE_VALUE};
+
+static struct arm_flash_dev_t ARM_FLASH0_DEV = {
+#if (__DOMAIN_NS == 1)
+    .memory_base = FLASH0_BASE_NS,
+#else
+    .memory_base = FLASH0_BASE_S,
+#endif /* __DOMAIN_NS == 1 */
+    .data        = &(ARM_FLASH0_DEV_DATA)};
+
+struct arm_flash_dev_t *FLASH0_DEV = &ARM_FLASH0_DEV;
+
+/*
+ * Functions
+ */
+
+static ARM_DRIVER_VERSION ARM_Flash_GetVersion(void)
+{
+    return DriverVersion;
+}
+
+static ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void)
+{
+    return DriverCapabilities;
+}
+
+static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event)
+{
+    ARG_UNUSED(cb_event);
+
+    if (DriverCapabilities.data_width >= DATA_WIDTH_ENUM_SIZE) {
+        return ARM_DRIVER_ERROR;
+    }
+
+    /* Nothing to be done */
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_Uninitialize(void)
+{
+    /* Nothing to be done */
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state) {
+    case ARM_POWER_FULL:
+        /* Nothing to be done */
+        return ARM_DRIVER_OK;
+        break;
+
+    case ARM_POWER_OFF:
+    case ARM_POWER_LOW:
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+static int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt)
+{
+    uint32_t start_addr = FLASH0_DEV->memory_base + addr;
+    int32_t rc = 0;
+
+    /* Conversion between data items and bytes */
+    cnt *= data_width_byte[DriverCapabilities.data_width];
+
+    /* Check flash memory boundaries */
+    rc = is_range_valid(FLASH0_DEV, addr + cnt);
+    if (rc != 0) {
+        return ARM_DRIVER_ERROR_PARAMETER;
+    }
+
+    /* Flash interface just emulated over SRAM, use memcpy */
+    memcpy(data, (void *)start_addr, cnt);
+
+    /* Conversion between bytes and data items */
+    cnt /= data_width_byte[DriverCapabilities.data_width];
+
+    return cnt;
+}
+
+static int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data,
+                                     uint32_t cnt)
+{
+    uint32_t start_addr = FLASH0_DEV->memory_base + addr;
+    int32_t rc = 0;
+
+    /* Conversion between data items and bytes */
+    cnt *= data_width_byte[DriverCapabilities.data_width];
+
+    /* Check flash memory boundaries and alignment with minimal write size */
+    rc  = is_range_valid(FLASH0_DEV, addr + cnt);
+    rc |= is_write_aligned(FLASH0_DEV, addr);
+    rc |= is_write_aligned(FLASH0_DEV, cnt);
+    if (rc != 0) {
+        return ARM_DRIVER_ERROR_PARAMETER;
+    }
+
+    /* Check if the flash area to write the data was erased previously */
+    rc = is_flash_ready_to_write((const uint8_t*)start_addr, cnt);
+    if (rc != 0) {
+        return ARM_DRIVER_ERROR;
+    }
+
+    /* Flash interface just emulated over SRAM, use memcpy */
+    memcpy((void *)start_addr, data, cnt);
+
+    /* Conversion between bytes and data items */
+    cnt /= data_width_byte[DriverCapabilities.data_width];
+
+    return cnt;
+}
+
+static int32_t ARM_Flash_EraseSector(uint32_t addr)
+{
+    uint32_t start_addr = FLASH0_DEV->memory_base + addr;
+    uint32_t rc = 0;
+
+    rc  = is_range_valid(FLASH0_DEV, addr);
+    rc |= is_sector_aligned(FLASH0_DEV, addr);
+    if (rc != 0) {
+        return ARM_DRIVER_ERROR_PARAMETER;
+    }
+
+    /* Flash interface just emulated over SRAM, use memset */
+    memset((void *)start_addr,
+           FLASH0_DEV->data->erased_value,
+           FLASH0_DEV->data->sector_size);
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_EraseChip(void)
+{
+    uint32_t i;
+    uint32_t addr = FLASH0_DEV->memory_base;
+    int32_t rc = ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    /* Check driver capability erase_chip bit */
+    if (DriverCapabilities.erase_chip == 1) {
+        for (i = 0; i < FLASH0_DEV->data->sector_count; i++) {
+            /* Flash interface just emulated over SRAM, use memset */
+            memset((void *)addr,
+                   FLASH0_DEV->data->erased_value,
+                   FLASH0_DEV->data->sector_size);
+
+            addr += FLASH0_DEV->data->sector_size;
+            rc = ARM_DRIVER_OK;
+        }
+    }
+    return rc;
+}
+
+static ARM_FLASH_STATUS ARM_Flash_GetStatus(void)
+{
+    return FlashStatus;
+}
+
+static ARM_FLASH_INFO * ARM_Flash_GetInfo(void)
+{
+    return FLASH0_DEV->data;
+}
+
+ARM_DRIVER_FLASH Driver_FLASH0 = {
+    ARM_Flash_GetVersion,
+    ARM_Flash_GetCapabilities,
+    ARM_Flash_Initialize,
+    ARM_Flash_Uninitialize,
+    ARM_Flash_PowerControl,
+    ARM_Flash_ReadData,
+    ARM_Flash_ProgramData,
+    ARM_Flash_EraseSector,
+    ARM_Flash_EraseChip,
+    ARM_Flash_GetStatus,
+    ARM_Flash_GetInfo
+};
+#endif /* RTE_FLASH0 */

bsp/tf_m_targets/arm/mps3/corstone_polaris/cmsis_drivers/Driver_PPC.h

+/*
+ * Copyright (c) 2019-2021 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __PPC_POLARIS_DRIVER_H__
+#define __PPC_POLARIS_DRIVER_H__
+
+#include "Driver_Common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* API version */
+#define ARM_PPC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)
+
+/* Security attribute used to configure the peripheral */
+typedef enum _PPC_POLARIS_SecAttr {
+    PPC_POLARIS_SECURE_CONFIG = 0,    /*!< Secure access */
+    PPC_POLARIS_NONSECURE_CONFIG,     /*!< Non-secure access */
+} PPC_POLARIS_SecAttr;
+
+/* Privilege attribute used to configure the peripheral */
+typedef enum _PPC_POLARIS_PrivAttr {
+    PPC_POLARIS_PRIV_AND_NONPRIV_CONFIG = 0, /*!< Privilege and non-privilege
+                                             * access */
+    PPC_POLARIS_PRIV_CONFIG,                 /*!< Privilege only access */
+} PPC_POLARIS_PrivAttr;
+
+/* Function descriptions */
+/**
+  SACFG  - Secure Privilege Control Block
+  NSACFG - Non-Secure Privilege Control Block
+
+  \fn          ARM_DRIVER_VERSION PPC_POLARIS_GetVersion(void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          int32_t PPC_POLARIS_Initialize(void)
+  \brief       Initializes PPC Interface.
+  \return      Returns Polaris PPC error code.
+
+  \fn          int32_t PPC_POLARIS_Uninitialize(void)
+  \brief       De-initializes PPC Interface.
+  \return      Returns Polaris PPC error code.
+
+  \fn          int32_t PPC_POLARIS_ConfigPrivilege(uint32_t periph,
+                                                  PPC_POLARIS_SecAttr sec_attr,
+                                                  PPC_POLARIS_PrivAttr priv_attr)
+  \brief       Configures privilege level with privileged and unprivileged
+               access or privileged access only in the given security domain
+               for a peripheral controlled by the given PPC.
+  \param[in]   periph:     Peripheral mask for SACFG and NSACFG registers.