Add U55 support for Corstone-310

Configuration has been moved outside of ml_interface.cpp into a
ethos-u55.h header which is included depending on the TS_TARGET
set.
ml_interface has been updated to enable timing addapters.

Signed-off-by: Vincent Coubard <vincent.coubard@arm.com>

bsp/CMakeLists.txt

@@ -88,6 +88,8 @@ target_include_directories(${LIB_NAME}
         ${PRJ_DIR}/bsp/aws_libraries/3rdparty/lwip_osal/include
         ${PRJ_DIR}/bsp/freertos-config
         ${PRJ_DIR}/bsp/freertos-platform
+        $<$<STREQUAL:${TS_TARGET},Corstone-300>:${CMAKE_CURRENT_SOURCE_DIR}/ethos-u55/an547>
+        $<$<STREQUAL:${TS_TARGET},Corstone-310>:${CMAKE_CURRENT_SOURCE_DIR}/ethos-u55/an555>
 )
 
 target_sources(${LIB_NAME}

bsp/ethos-u55/an547/ethos-u55.h

+/* Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ETHOS_U55_H_
+#define ETHOS_U55_H_
+
+#define EthosU_IRQn            (56)         /* Ethos-Uxx Interrupt */
+#define SEC_ETHOS_U55_BASE     (0x48102000) /* Ethos-U55 base address*/
+#define SEC_ETHOS_U55_TA0_BASE (0x48103000) /* Ethos-U55's timing adapter 0 base address */
+#define SEC_ETHOS_U55_TA1_BASE (0x48103200) /* Ethos-U55's timing adapter 1 base address */
+
+/* TA0 configuration */
+#define TA0_BASE      SEC_ETHOS_U55_TA0_BASE
+#define TA0_MAXR      0
+#define TA0_MAXW      0
+#define TA0_MAXRW     0
+#define TA0_RLATENCY  0
+#define TA0_WLATENCY  0
+#define TA0_PULSE_ON  0
+#define TA0_PULSE_OFF 0
+#define TA0_BWCAP     0
+#define TA0_PERFCTRL  0
+#define TA0_PERFCNT   0
+#define TA0_MODE      1
+#define TA0_HISTBIN   0
+#define TA0_HISTCNT   0
+
+/* TA1 configuration */
+#define TA1_BASE      SEC_ETHOS_U55_TA1_BASE
+#define TA1_MAXR      0
+#define TA1_MAXW      0
+#define TA1_MAXRW     0
+#define TA1_RLATENCY  0
+#define TA1_WLATENCY  0
+#define TA1_PULSE_ON  0
+#define TA1_PULSE_OFF 0
+#define TA1_BWCAP     0
+#define TA1_PERFCTRL  0
+#define TA1_PERFCNT   0
+#define TA1_MODE      1
+#define TA1_HISTBIN   0
+#define TA1_HISTCNT   0
+
+#endif ETHOS_U55_H_

bsp/ethos-u55/an555/ethos-u55.h

+/* Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ETHOS_U55_H_
+#define ETHOS_U55_H_
+
+#define EthosU_IRQn            (16)         /* Ethos-Uxx Interrupt */
+#define SEC_ETHOS_U55_BASE     (0x40004000) /* Ethos-U55 base address*/
+#define SEC_ETHOS_U55_TA0_BASE (0x48103000) /* Ethos-U55's timing adapter 0 base address */
+#define SEC_ETHOS_U55_TA1_BASE (0x48103200) /* Ethos-U55's timing adapter 1 base address */
+
+/* TA0 configuration */
+#define TA0_BASE      SEC_ETHOS_U55_TA0_BASE
+#define TA0_MAXR      0
+#define TA0_MAXW      0
+#define TA0_MAXRW     0
+#define TA0_RLATENCY  0
+#define TA0_WLATENCY  0
+#define TA0_PULSE_ON  0
+#define TA0_PULSE_OFF 0
+#define TA0_BWCAP     0
+#define TA0_PERFCTRL  0
+#define TA0_PERFCNT   0
+#define TA0_MODE      1
+#define TA0_HISTBIN   0
+#define TA0_HISTCNT   0
+
+/* TA1 configuration */
+#define TA1_BASE      SEC_ETHOS_U55_TA1_BASE
+#define TA1_MAXR      0
+#define TA1_MAXW      0
+#define TA1_MAXRW     0
+#define TA1_RLATENCY  0
+#define TA1_WLATENCY  0
+#define TA1_PULSE_ON  0
+#define TA1_PULSE_OFF 0
+#define TA1_BWCAP     0
+#define TA1_PERFCTRL  0
+#define TA1_PERFCNT   0
+#define TA1_MODE      1
+#define TA1_HISTBIN   0
+#define TA1_HISTCNT   0
+
+#endif /* ETHOS_U55_H_ */

kws/CMakeLists.txt

-# Copyright (c) 2021 ARM Limited. All rights reserved.
+# Copyright (c) 2021-2022 ARM Limited. All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
 cmake_minimum_required(VERSION 3.21)
@@ -124,6 +124,7 @@ target_include_directories(kws
         ${ml-embedded-evaluation-kit_GENERATED_DIR}/kws/include/
         ${ml-embedded-evaluation-kit_SOURCE_DIR}/dependencies/cmsis/CMSIS/DSP/Include
         ${ml-embedded-evaluation-kit_SOURCE_DIR}/dependencies/core-driver/include
+        ${ml-embedded-evaluation-kit_SOURCE_DIR}/dependencies/core-software/drivers/timing_adapter/include
         ${ml-embedded-evaluation-kit_SOURCE_DIR}/dependencies/tensorflow
         ${ml-embedded-evaluation-kit_SOURCE_DIR}/dependencies/tensorflow/tensorflow/lite/micro
         ${ml-embedded-evaluation-kit_SOURCE_DIR}/dependencies/tensorflow/tensorflow/lite/micro/tools/make/downloads/flatbuffers/include

kws/source/ml_interface.cc

 /*
- * Copyright (c) 2021 Arm Limited
+ * Copyright (c) 2021-2022 Arm Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -35,17 +35,15 @@
 #include "UseCaseCommonUtils.hpp"
 #include "audio_processing.h"
 
-#define EthosU_IRQn            (56)         /* Ethos-Uxx Interrupt */
-#define SEC_ETHOS_U55_BASE     (0x48102000) /* Ethos-U55 base address*/
-#define SEC_ETHOS_U55_TA0_BASE (0x48103000) /* Ethos-U55's timing adapter 0 base address */
-#define SEC_ETHOS_U55_TA1_BASE (0x48103200) /* Ethos-U55's timing adapter 1 base address */
+#include "ethos-u55.h" /* Mem map and configuration definitions of the Ethos U55 */
 
 #include "smm_mps3.h"    /* Mem map for MPS3 peripherals. */
 #include "glcd_mps3.h"   /* LCD functions. */
 #include "timer_mps3.h"  /* Timer functions. */
 #include "device_mps3.h" /* FPGA level definitions and functions. */
 
-#include "ethosu_driver.h" /* Arm Ethos-U55 driver header */
+#include "ethosu_driver.h"  /* Arm Ethos-U55 driver header */
+#include "timing_adapter.h" /* Driver header of the timing adapter */
 
 #include "hal.h"
 #include <vector>