i2c-i801.c 59.1 KB
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
    Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
    Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
    <mdsxyz123@yahoo.com>
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    Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
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    Copyright (C) 2010         Intel Corporation,
                               David Woodhouse <dwmw2@infradead.org>
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*/

/*
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 * Supports the following Intel I/O Controller Hubs (ICH):
 *
 *					I/O			Block	I2C
 *					region	SMBus	Block	proc.	block
 * Chip name			PCI ID	size	PEC	buffer	call	read
 * ---------------------------------------------------------------------------
 * 82801AA (ICH)		0x2413	16	no	no	no	no
 * 82801AB (ICH0)		0x2423	16	no	no	no	no
 * 82801BA (ICH2)		0x2443	16	no	no	no	no
 * 82801CA (ICH3)		0x2483	32	soft	no	no	no
 * 82801DB (ICH4)		0x24c3	32	hard	yes	no	no
 * 82801E (ICH5)		0x24d3	32	hard	yes	yes	yes
 * 6300ESB			0x25a4	32	hard	yes	yes	yes
 * 82801F (ICH6)		0x266a	32	hard	yes	yes	yes
 * 6310ESB/6320ESB		0x269b	32	hard	yes	yes	yes
 * 82801G (ICH7)		0x27da	32	hard	yes	yes	yes
 * 82801H (ICH8)		0x283e	32	hard	yes	yes	yes
 * 82801I (ICH9)		0x2930	32	hard	yes	yes	yes
 * EP80579 (Tolapai)		0x5032	32	hard	yes	yes	yes
 * ICH10			0x3a30	32	hard	yes	yes	yes
 * ICH10			0x3a60	32	hard	yes	yes	yes
 * 5/3400 Series (PCH)		0x3b30	32	hard	yes	yes	yes
 * 6 Series (PCH)		0x1c22	32	hard	yes	yes	yes
 * Patsburg (PCH)		0x1d22	32	hard	yes	yes	yes
 * Patsburg (PCH) IDF		0x1d70	32	hard	yes	yes	yes
 * Patsburg (PCH) IDF		0x1d71	32	hard	yes	yes	yes
 * Patsburg (PCH) IDF		0x1d72	32	hard	yes	yes	yes
 * DH89xxCC (PCH)		0x2330	32	hard	yes	yes	yes
 * Panther Point (PCH)		0x1e22	32	hard	yes	yes	yes
 * Lynx Point (PCH)		0x8c22	32	hard	yes	yes	yes
 * Lynx Point-LP (PCH)		0x9c22	32	hard	yes	yes	yes
 * Avoton (SOC)			0x1f3c	32	hard	yes	yes	yes
 * Wellsburg (PCH)		0x8d22	32	hard	yes	yes	yes
 * Wellsburg (PCH) MS		0x8d7d	32	hard	yes	yes	yes
 * Wellsburg (PCH) MS		0x8d7e	32	hard	yes	yes	yes
 * Wellsburg (PCH) MS		0x8d7f	32	hard	yes	yes	yes
 * Coleto Creek (PCH)		0x23b0	32	hard	yes	yes	yes
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 * Wildcat Point (PCH)		0x8ca2	32	hard	yes	yes	yes
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 * Wildcat Point-LP (PCH)	0x9ca2	32	hard	yes	yes	yes
 * BayTrail (SOC)		0x0f12	32	hard	yes	yes	yes
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 * Braswell (SOC)		0x2292	32	hard	yes	yes	yes
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 * Sunrise Point-H (PCH) 	0xa123  32	hard	yes	yes	yes
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 * Sunrise Point-LP (PCH)	0x9d23	32	hard	yes	yes	yes
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 * DNV (SOC)			0x19df	32	hard	yes	yes	yes
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 * Emmitsburg (PCH)		0x1bc9	32	hard	yes	yes	yes
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 * Broxton (SOC)		0x5ad4	32	hard	yes	yes	yes
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 * Lewisburg (PCH)		0xa1a3	32	hard	yes	yes	yes
 * Lewisburg Supersku (PCH)	0xa223	32	hard	yes	yes	yes
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 * Kaby Lake PCH-H (PCH)	0xa2a3	32	hard	yes	yes	yes
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 * Gemini Lake (SOC)		0x31d4	32	hard	yes	yes	yes
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 * Cannon Lake-H (PCH)		0xa323	32	hard	yes	yes	yes
 * Cannon Lake-LP (PCH)		0x9da3	32	hard	yes	yes	yes
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 * Cedar Fork (PCH)		0x18df	32	hard	yes	yes	yes
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 * Ice Lake-LP (PCH)		0x34a3	32	hard	yes	yes	yes
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 * Comet Lake (PCH)		0x02a3	32	hard	yes	yes	yes
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 * Comet Lake-H (PCH)		0x06a3	32	hard	yes	yes	yes
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 * Elkhart Lake (PCH)		0x4b23	32	hard	yes	yes	yes
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 * Tiger Lake-LP (PCH)		0xa0a3	32	hard	yes	yes	yes
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 * Tiger Lake-H (PCH)		0x43a3	32	hard	yes	yes	yes
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 * Jasper Lake (SOC)		0x4da3	32	hard	yes	yes	yes
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 * Comet Lake-V (PCH)		0xa3a3	32	hard	yes	yes	yes
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 * Alder Lake-S (PCH)		0x7aa3	32	hard	yes	yes	yes
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 * Alder Lake-P (PCH)		0x51a3	32	hard	yes	yes	yes
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 * Alder Lake-M (PCH)		0x54a3	32	hard	yes	yes	yes
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 *
 * Features supported by this driver:
 * Software PEC				no
 * Hardware PEC				yes
 * Block buffer				yes
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 * Block process call transaction	yes
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 * I2C block read transaction		yes (doesn't use the block buffer)
 * Slave mode				no
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 * SMBus Host Notify			yes
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 * Interrupt processing			yes
 *
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 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
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 */
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#include <linux/interrupt.h>
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#include <linux/module.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/stddef.h>
#include <linux/delay.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/i2c.h>
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#include <linux/i2c-smbus.h>
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#include <linux/acpi.h>
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#include <linux/io.h>
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#include <linux/dmi.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/wait.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
#include <linux/platform_data/itco_wdt.h>
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#include <linux/pm_runtime.h>
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#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
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#include <linux/gpio/machine.h>
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#include <linux/platform_data/i2c-mux-gpio.h>
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#endif
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/* I801 SMBus address offsets */
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#define SMBHSTSTS(p)	(0 + (p)->smba)
#define SMBHSTCNT(p)	(2 + (p)->smba)
#define SMBHSTCMD(p)	(3 + (p)->smba)
#define SMBHSTADD(p)	(4 + (p)->smba)
#define SMBHSTDAT0(p)	(5 + (p)->smba)
#define SMBHSTDAT1(p)	(6 + (p)->smba)
#define SMBBLKDAT(p)	(7 + (p)->smba)
#define SMBPEC(p)	(8 + (p)->smba)		/* ICH3 and later */
#define SMBAUXSTS(p)	(12 + (p)->smba)	/* ICH4 and later */
#define SMBAUXCTL(p)	(13 + (p)->smba)	/* ICH4 and later */
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#define SMBSLVSTS(p)	(16 + (p)->smba)	/* ICH3 and later */
#define SMBSLVCMD(p)	(17 + (p)->smba)	/* ICH3 and later */
#define SMBNTFDADD(p)	(20 + (p)->smba)	/* ICH3 and later */
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/* PCI Address Constants */
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#define SMBBAR		4
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#define SMBPCICTL	0x004
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#define SMBPCISTS	0x006
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#define SMBHSTCFG	0x040
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#define TCOBASE		0x050
#define TCOCTL		0x054

#define SBREG_BAR		0x10
#define SBREG_SMBCTRL		0xc6000c
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#define SBREG_SMBCTRL_DNV	0xcf000c
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/* Host status bits for SMBPCISTS */
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#define SMBPCISTS_INTS		BIT(3)
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/* Control bits for SMBPCICTL */
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#define SMBPCICTL_INTDIS	BIT(10)
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/* Host configuration bits for SMBHSTCFG */
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#define SMBHSTCFG_HST_EN	BIT(0)
#define SMBHSTCFG_SMB_SMI_EN	BIT(1)
#define SMBHSTCFG_I2C_EN	BIT(2)
#define SMBHSTCFG_SPD_WD	BIT(4)
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/* TCO configuration bits for TCOCTL */
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#define TCOCTL_EN		BIT(8)
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/* Auxiliary status register bits, ICH4+ only */
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#define SMBAUXSTS_CRCE		BIT(0)
#define SMBAUXSTS_STCO		BIT(1)
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/* Auxiliary control register bits, ICH4+ only */
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#define SMBAUXCTL_CRC		BIT(0)
#define SMBAUXCTL_E32B		BIT(1)
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/* Other settings */
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#define MAX_RETRIES		400
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/* I801 command constants */
#define I801_QUICK		0x00
#define I801_BYTE		0x04
#define I801_BYTE_DATA		0x08
#define I801_WORD_DATA		0x0C
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#define I801_PROC_CALL		0x10	/* unimplemented */
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#define I801_BLOCK_DATA		0x14
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#define I801_I2C_BLOCK_DATA	0x18	/* ICH5 and later */
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#define I801_BLOCK_PROC_CALL	0x1C
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/* I801 Host Control register bits */
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#define SMBHSTCNT_INTREN	BIT(0)
#define SMBHSTCNT_KILL		BIT(1)
#define SMBHSTCNT_LAST_BYTE	BIT(5)
#define SMBHSTCNT_START		BIT(6)
#define SMBHSTCNT_PEC_EN	BIT(7)	/* ICH3 and later */
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/* I801 Hosts Status register bits */
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#define SMBHSTSTS_BYTE_DONE	BIT(7)
#define SMBHSTSTS_INUSE_STS	BIT(6)
#define SMBHSTSTS_SMBALERT_STS	BIT(5)
#define SMBHSTSTS_FAILED	BIT(4)
#define SMBHSTSTS_BUS_ERR	BIT(3)
#define SMBHSTSTS_DEV_ERR	BIT(2)
#define SMBHSTSTS_INTR		BIT(1)
#define SMBHSTSTS_HOST_BUSY	BIT(0)
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/* Host Notify Status register bits */
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#define SMBSLVSTS_HST_NTFY_STS	BIT(0)
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/* Host Notify Command register bits */
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#define SMBSLVCMD_HST_NTFY_INTREN	BIT(0)
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#define STATUS_ERROR_FLAGS	(SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
				 SMBHSTSTS_DEV_ERR)

#define STATUS_FLAGS		(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
				 STATUS_ERROR_FLAGS)
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/* Older devices have their ID defined in <linux/pci_ids.h> */
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#define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS		0x02a3
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#define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS		0x06a3
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#define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS		0x0f12
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#define PCI_DEVICE_ID_INTEL_CDF_SMBUS			0x18df
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#define PCI_DEVICE_ID_INTEL_DNV_SMBUS			0x19df
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#define PCI_DEVICE_ID_INTEL_EBG_SMBUS			0x1bc9
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#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS		0x1c22
#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS		0x1d22
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/* Patsburg also has three 'Integrated Device Function' SMBus controllers */
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#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0		0x1d70
#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1		0x1d71
#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2		0x1d72
#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS		0x1e22
#define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS		0x1f3c
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#define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS		0x2292
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#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS		0x2330
#define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS		0x23b0
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#define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS		0x31d4
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#define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS		0x34a3
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#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS		0x3b30
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#define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS		0x43a3
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#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS		0x4b23
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#define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS		0x4da3
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#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS		0x51a3
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#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS		0x54a3
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#define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS		0x5ad4
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#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS		0x7aa3
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS		0x8c22
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#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS		0x8ca2
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#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS		0x8d22
#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0		0x8d7d
#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1		0x8d7e
#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2		0x8d7f
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS		0x9c22
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#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS	0x9ca2
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS	0x9d23
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#define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS		0x9da3
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#define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS		0xa0a3
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS	0xa123
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#define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS		0xa1a3
#define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS	0xa223
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#define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS	0xa2a3
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#define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS		0xa323
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#define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS		0xa3a3
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struct i801_mux_config {
	char *gpio_chip;
	unsigned values[3];
	int n_values;
	unsigned classes[3];
	unsigned gpios[2];		/* Relative to gpio_chip->base */
	int n_gpios;
};

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struct i801_priv {
	struct i2c_adapter adapter;
	unsigned long smba;
	unsigned char original_hstcfg;
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	unsigned char original_slvcmd;
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	struct pci_dev *pci_dev;
	unsigned int features;
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	/* isr processing */
	wait_queue_head_t waitq;
	u8 status;
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	/* Command state used by isr for byte-by-byte block transactions */
	u8 cmd;
	bool is_read;
	int count;
	int len;
	u8 *data;
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#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
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	const struct i801_mux_config *mux_drvdata;
	struct platform_device *mux_pdev;
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	struct gpiod_lookup_table *lookup;
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#endif
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	struct platform_device *tco_pdev;
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	/*
	 * If set to true the host controller registers are reserved for
	 * ACPI AML use. Protected by acpi_lock.
	 */
	bool acpi_reserved;
	struct mutex acpi_lock;
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};

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#define FEATURE_SMBUS_PEC	BIT(0)
#define FEATURE_BLOCK_BUFFER	BIT(1)
#define FEATURE_BLOCK_PROC	BIT(2)
#define FEATURE_I2C_BLOCK_READ	BIT(3)
#define FEATURE_IRQ		BIT(4)
#define FEATURE_HOST_NOTIFY	BIT(5)
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/* Not really a feature, but it's convenient to handle it as such */
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#define FEATURE_IDF		BIT(15)
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#define FEATURE_TCO_SPT		BIT(16)
#define FEATURE_TCO_CNL		BIT(17)
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static const char *i801_feature_names[] = {
	"SMBus PEC",
	"Block buffer",
	"Block process call",
	"I2C block read",
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	"Interrupt",
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	"SMBus Host Notify",
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};

static unsigned int disable_features;
module_param(disable_features, uint, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
	"\t\t  0x01  disable SMBus PEC\n"
	"\t\t  0x02  disable the block buffer\n"
	"\t\t  0x08  disable the I2C block read functionality\n"
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	"\t\t  0x10  don't use interrupts\n"
	"\t\t  0x20  disable SMBus Host Notify ");
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/* Make sure the SMBus host is ready to start transmitting.
   Return 0 if it is, -EBUSY if it is not. */
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static int i801_check_pre(struct i801_priv *priv)
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{
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	int status;
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	status = inb_p(SMBHSTSTS(priv));
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	if (status & SMBHSTSTS_HOST_BUSY) {
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		dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
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		return -EBUSY;
	}

	status &= STATUS_FLAGS;
	if (status) {
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		dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
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			status);
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		outb_p(status, SMBHSTSTS(priv));
		status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
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		if (status) {
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			dev_err(&priv->pci_dev->dev,
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				"Failed clearing status flags (%02x)\n",
				status);
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			return -EBUSY;
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		}
	}

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	/*
	 * Clear CRC status if needed.
	 * During normal operation, i801_check_post() takes care
	 * of it after every operation.  We do it here only in case
	 * the hardware was already in this state when the driver
	 * started.
	 */
	if (priv->features & FEATURE_SMBUS_PEC) {
		status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
		if (status) {
			dev_dbg(&priv->pci_dev->dev,
				"Clearing aux status flags (%02x)\n", status);
			outb_p(status, SMBAUXSTS(priv));
			status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
			if (status) {
				dev_err(&priv->pci_dev->dev,
					"Failed clearing aux status flags (%02x)\n",
					status);
				return -EBUSY;
			}
		}
	}

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	return 0;
}
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/*
 * Convert the status register to an error code, and clear it.
 * Note that status only contains the bits we want to clear, not the
 * actual register value.
 */
static int i801_check_post(struct i801_priv *priv, int status)
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{
	int result = 0;
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	/*
	 * If the SMBus is still busy, we give up
	 * Note: This timeout condition only happens when using polling
	 * transactions.  For interrupt operation, NAK/timeout is indicated by
	 * DEV_ERR.
	 */
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	if (unlikely(status < 0)) {
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		dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
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		/* try to stop the current command */
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		dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
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		outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
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		usleep_range(1000, 2000);
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		outb_p(0, SMBHSTCNT(priv));
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		/* Check if it worked */
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		status = inb_p(SMBHSTSTS(priv));
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		if ((status & SMBHSTSTS_HOST_BUSY) ||
		    !(status & SMBHSTSTS_FAILED))
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			dev_err(&priv->pci_dev->dev,
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				"Failed terminating the transaction\n");
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		outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
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		return -ETIMEDOUT;
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	}

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	if (status & SMBHSTSTS_FAILED) {
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		result = -EIO;
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		dev_err(&priv->pci_dev->dev, "Transaction failed\n");
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	}
	if (status & SMBHSTSTS_DEV_ERR) {
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		/*
		 * This may be a PEC error, check and clear it.
		 *
		 * AUXSTS is handled differently from HSTSTS.
		 * For HSTSTS, i801_isr() or i801_wait_intr()
		 * has already cleared the error bits in hardware,
		 * and we are passed a copy of the original value
		 * in "status".
		 * For AUXSTS, the hardware register is left
		 * for us to handle here.
		 * This is asymmetric, slightly iffy, but safe,
		 * since all this code is serialized and the CRCE
		 * bit is harmless as long as it's cleared before
		 * the next operation.
		 */
		if ((priv->features & FEATURE_SMBUS_PEC) &&
		    (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
			outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
			result = -EBADMSG;
			dev_dbg(&priv->pci_dev->dev, "PEC error\n");
		} else {
			result = -ENXIO;
			dev_dbg(&priv->pci_dev->dev, "No response\n");
		}
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	}
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	if (status & SMBHSTSTS_BUS_ERR) {
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		result = -EAGAIN;
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		dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
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	}

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	/* Clear status flags except BYTE_DONE, to be cleared by caller */
	outb_p(status, SMBHSTSTS(priv));
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	return result;
}

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/* Wait for BUSY being cleared and either INTR or an error flag being set */
static int i801_wait_intr(struct i801_priv *priv)
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{
	int timeout = 0;
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	int status;
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	/* We will always wait for a fraction of a second! */
	do {
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		usleep_range(250, 500);
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		status = inb_p(SMBHSTSTS(priv));
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	} while (((status & SMBHSTSTS_HOST_BUSY) ||
		  !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
		 (timeout++ < MAX_RETRIES));
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	if (timeout > MAX_RETRIES) {
		dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
		return -ETIMEDOUT;
	}
	return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
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}

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/* Wait for either BYTE_DONE or an error flag being set */
static int i801_wait_byte_done(struct i801_priv *priv)
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{
	int timeout = 0;
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	int status;
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	/* We will always wait for a fraction of a second! */
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	do {
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		usleep_range(250, 500);
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		status = inb_p(SMBHSTSTS(priv));
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	} while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
		 (timeout++ < MAX_RETRIES));

	if (timeout > MAX_RETRIES) {
		dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
		return -ETIMEDOUT;
	}
	return status & STATUS_ERROR_FLAGS;
}

static int i801_transaction(struct i801_priv *priv, int xact)
{
	int status;
	int result;
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	const struct i2c_adapter *adap = &priv->adapter;
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	result = i801_check_pre(priv);
	if (result < 0)
		return result;
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	if (priv->features & FEATURE_IRQ) {
		outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
		       SMBHSTCNT(priv));
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		result = wait_event_timeout(priv->waitq,
					    (status = priv->status),
					    adap->timeout);
		if (!result) {
			status = -ETIMEDOUT;
			dev_warn(&priv->pci_dev->dev,
				 "Timeout waiting for interrupt!\n");
		}
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		priv->status = 0;
		return i801_check_post(priv, status);
	}

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	/* the current contents of SMBHSTCNT can be overwritten, since PEC,
	 * SMBSCMD are passed in xact */
	outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));

	status = i801_wait_intr(priv);
	return i801_check_post(priv, status);
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}

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static int i801_block_transaction_by_block(struct i801_priv *priv,
					   union i2c_smbus_data *data,
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					   char read_write, int command,
					   int hwpec)
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{
	int i, len;
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	int status;
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	int xact = hwpec ? SMBHSTCNT_PEC_EN : 0;

	switch (command) {
	case I2C_SMBUS_BLOCK_PROC_CALL:
		xact |= I801_BLOCK_PROC_CALL;
		break;
	case I2C_SMBUS_BLOCK_DATA:
		xact |= I801_BLOCK_DATA;
		break;
	default:
		return -EOPNOTSUPP;
	}
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	inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
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	/* Use 32-byte buffer to process this transaction */
	if (read_write == I2C_SMBUS_WRITE) {
		len = data->block[0];
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		outb_p(len, SMBHSTDAT0(priv));
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		for (i = 0; i < len; i++)
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			outb_p(data->block[i+1], SMBBLKDAT(priv));
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	}

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	status = i801_transaction(priv, xact);
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	if (status)
		return status;
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	if (read_write == I2C_SMBUS_READ ||
	    command == I2C_SMBUS_BLOCK_PROC_CALL) {
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		len = inb_p(SMBHSTDAT0(priv));
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		if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
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			return -EPROTO;
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		data->block[0] = len;
		for (i = 0; i < len; i++)
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			data->block[i + 1] = inb_p(SMBBLKDAT(priv));
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	}
	return 0;
}

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static void i801_isr_byte_done(struct i801_priv *priv)
{
	if (priv->is_read) {
		/* For SMBus block reads, length is received with first byte */
		if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
		    (priv->count == 0)) {
			priv->len = inb_p(SMBHSTDAT0(priv));
			if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
				dev_err(&priv->pci_dev->dev,
					"Illegal SMBus block read size %d\n",
					priv->len);
				/* FIXME: Recover */
				priv->len = I2C_SMBUS_BLOCK_MAX;
			} else {
				dev_dbg(&priv->pci_dev->dev,
					"SMBus block read size is %d\n",
					priv->len);
			}
			priv->data[-1] = priv->len;
		}

		/* Read next byte */
		if (priv->count < priv->len)
			priv->data[priv->count++] = inb(SMBBLKDAT(priv));
		else
			dev_dbg(&priv->pci_dev->dev,
				"Discarding extra byte on block read\n");

		/* Set LAST_BYTE for last byte of read transaction */
		if (priv->count == priv->len - 1)
			outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
			       SMBHSTCNT(priv));
	} else if (priv->count < priv->len - 1) {
		/* Write next byte, except for IRQ after last byte */
		outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
	}

	/* Clear BYTE_DONE to continue with next byte */
	outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
}

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static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
{
	unsigned short addr;

	addr = inb_p(SMBNTFDADD(priv)) >> 1;

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	/*
	 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
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	 * always returns 0. Our current implementation doesn't provide
	 * data, so we just ignore it.
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	 */
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	i2c_handle_smbus_host_notify(&priv->adapter, addr);
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	/* clear Host Notify bit and return */
	outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
	return IRQ_HANDLED;
}

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/*
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 * There are three kinds of interrupts:
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 *
 * 1) i801 signals transaction completion with one of these interrupts:
 *      INTR - Success
 *      DEV_ERR - Invalid command, NAK or communication timeout
 *      BUS_ERR - SMI# transaction collision
 *      FAILED - transaction was canceled due to a KILL request
 *    When any of these occur, update ->status and wake up the waitq.
 *    ->status must be cleared before kicking off the next transaction.
 *
 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 *    occurs for each byte of a byte-by-byte to prepare the next byte.
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 *
 * 3) Host Notify interrupts
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 */
static irqreturn_t i801_isr(int irq, void *dev_id)
{
	struct i801_priv *priv = dev_id;
	u16 pcists;
	u8 status;

	/* Confirm this is our interrupt */
	pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
	if (!(pcists & SMBPCISTS_INTS))
		return IRQ_NONE;

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	if (priv->features & FEATURE_HOST_NOTIFY) {
		status = inb_p(SMBSLVSTS(priv));
		if (status & SMBSLVSTS_HST_NTFY_STS)
			return i801_host_notify_isr(priv);
	}

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	status = inb_p(SMBHSTSTS(priv));
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	if (status & SMBHSTSTS_BYTE_DONE)
		i801_isr_byte_done(priv);

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	/*
	 * Clear irq sources and report transaction result.
	 * ->status must be cleared before the next transaction is started.
	 */
	status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
	if (status) {
		outb_p(status, SMBHSTSTS(priv));
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		priv->status = status;
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		wake_up(&priv->waitq);
	}

	return IRQ_HANDLED;
}

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/*
 * For "byte-by-byte" block transactions:
 *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 */
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static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
					       union i2c_smbus_data *data,
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					       char read_write, int command,
					       int hwpec)
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{
	int i, len;
	int smbcmd;
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	int status;
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	int result;
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	const struct i2c_adapter *adap = &priv->adapter;
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	if (command == I2C_SMBUS_BLOCK_PROC_CALL)
		return -EOPNOTSUPP;

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	result = i801_check_pre(priv);
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	if (result < 0)
		return result;
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	len = data->block[0];
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	if (read_write == I2C_SMBUS_WRITE) {
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		outb_p(len, SMBHSTDAT0(priv));
		outb_p(data->block[1], SMBBLKDAT(priv));
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	}

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	if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
	    read_write == I2C_SMBUS_READ)
		smbcmd = I801_I2C_BLOCK_DATA;
	else
		smbcmd = I801_BLOCK_DATA;

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	if (priv->features & FEATURE_IRQ) {
		priv->is_read = (read_write == I2C_SMBUS_READ);
		if (len == 1 && priv->is_read)
			smbcmd |= SMBHSTCNT_LAST_BYTE;
		priv->cmd = smbcmd | SMBHSTCNT_INTREN;
		priv->len = len;
		priv->count = 0;
		priv->data = &data->block[1];

		outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
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		result = wait_event_timeout(priv->waitq,
					    (status = priv->status),
					    adap->timeout);
		if (!result) {
			status = -ETIMEDOUT;
			dev_warn(&priv->pci_dev->dev,
				 "Timeout waiting for interrupt!\n");
		}
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		priv->status = 0;
		return i801_check_post(priv, status);
	}

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	for (i = 1; i <= len; i++) {
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		if (i == len && read_write == I2C_SMBUS_READ)
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			smbcmd |= SMBHSTCNT_LAST_BYTE;
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		outb_p(smbcmd, SMBHSTCNT(priv));
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		if (i == 1)
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			outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
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			       SMBHSTCNT(priv));
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		status = i801_wait_byte_done(priv);
		if (status)
			goto exit;
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		if (i == 1 && read_write == I2C_SMBUS_READ
		 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
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			len = inb_p(SMBHSTDAT0(priv));
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			if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
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				dev_err(&priv->pci_dev->dev,
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					"Illegal SMBus block read size %d\n",
					len);
				/* Recover */
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				while (inb_p(SMBHSTSTS(priv)) &
				       SMBHSTSTS_HOST_BUSY)
					outb_p(SMBHSTSTS_BYTE_DONE,
					       SMBHSTSTS(priv));
				outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
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				return -EPROTO;
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			}
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			data->block[0] = len;
		}

		/* Retrieve/store value in SMBBLKDAT */
		if (read_write == I2C_SMBUS_READ)
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			data->block[i] = inb_p(SMBBLKDAT(priv));
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		if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
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			outb_p(data->block[i+1], SMBBLKDAT(priv));
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		/* signals SMBBLKDAT ready */
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		outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
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	}
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	status = i801_wait_intr(priv);
exit:
	return i801_check_post(priv, status);
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}
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static int i801_set_block_buffer_mode(struct i801_priv *priv)
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{
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	outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
	if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
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		return -EIO;
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	return 0;
}

/* Block transaction function */
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static int i801_block_transaction(struct i801_priv *priv,
				  union i2c_smbus_data *data, char read_write,
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				  int command, int hwpec)
{
	int result = 0;
	unsigned char hostc;

	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
		if (read_write == I2C_SMBUS_WRITE) {
			/* set I2C_EN bit in configuration register */
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			pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
			pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
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					      hostc | SMBHSTCFG_I2C_EN);
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		} else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
			dev_err(&priv->pci_dev->dev,
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				"I2C block read is unsupported!\n");
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			return -EOPNOTSUPP;
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		}
	}

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	if (read_write == I2C_SMBUS_WRITE
	 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
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		if (data->block[0] < 1)
			data->block[0] = 1;
		if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
			data->block[0] = I2C_SMBUS_BLOCK_MAX;
	} else {
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		data->block[0] = 32;	/* max for SMBus block reads */
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	}

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	/* Experience has shown that the block buffer can only be used for
	   SMBus (not I2C) block transactions, even though the datasheet
	   doesn't mention this limitation. */
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	if ((priv->features & FEATURE_BLOCK_BUFFER)
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	 && command != I2C_SMBUS_I2C_BLOCK_DATA
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	 && i801_set_block_buffer_mode(priv) == 0)
		result = i801_block_transaction_by_block(priv, data,
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							 read_write,
							 command, hwpec);
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	else
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		result = i801_block_transaction_byte_by_byte(priv, data,
							     read_write,
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							     command, hwpec);
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	if (command == I2C_SMBUS_I2C_BLOCK_DATA
	 && read_write == I2C_SMBUS_WRITE) {
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		/* restore saved configuration register value */
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		pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
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	}
	return result;
}

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/* Return negative errno on error. */
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static s32 i801_access(struct i2c_adapter *adap, u16 addr,
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		       unsigned short flags, char read_write, u8 command,
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		       int size, union i2c_smbus_data *data)
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{
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	int hwpec;
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	int block = 0;
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	int ret = 0, xact = 0;
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	struct i801_priv *priv = i2c_get_adapdata(adap);
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	mutex_lock(&priv->acpi_lock);
	if (priv->acpi_reserved) {
		mutex_unlock(&priv->acpi_lock);
		return -EBUSY;
	}

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	pm_runtime_get_sync(&priv->pci_dev->dev);

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	hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
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		&& size != I2C_SMBUS_QUICK
		&& size != I2C_SMBUS_I2C_BLOCK_DATA;
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	switch (size) {
	case I2C_SMBUS_QUICK:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
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		       SMBHSTADD(priv));
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		xact = I801_QUICK;
		break;
	case I2C_SMBUS_BYTE:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
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		       SMBHSTADD(priv));
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		if (read_write == I2C_SMBUS_WRITE)
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			outb_p(command, SMBHSTCMD(priv));
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		xact = I801_BYTE;
		break;
	case I2C_SMBUS_BYTE_DATA:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
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		       SMBHSTADD(priv));
		outb_p(command, SMBHSTCMD(priv));
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		if (read_write == I2C_SMBUS_WRITE)
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			outb_p(data->byte, SMBHSTDAT0(priv));
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		xact = I801_BYTE_DATA;
		break;
	case I2C_SMBUS_WORD_DATA:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
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		       SMBHSTADD(priv));
		outb_p(command, SMBHSTCMD(priv));
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		if (read_write == I2C_SMBUS_WRITE) {
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			outb_p(data->word & 0xff, SMBHSTDAT0(priv));
			outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
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		}
		xact = I801_WORD_DATA;
		break;
	case I2C_SMBUS_BLOCK_DATA:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
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		       SMBHSTADD(priv));
		outb_p(command, SMBHSTCMD(priv));
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		block = 1;
		break;
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	case I2C_SMBUS_I2C_BLOCK_DATA:
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		/*
		 * NB: page 240 of ICH5 datasheet shows that the R/#W
		 * bit should be cleared here, even when reading.
		 * However if SPD Write Disable is set (Lynx Point and later),
		 * the read will fail if we don't set the R/#W bit.
		 */
		outb_p(((addr & 0x7f) << 1) |
		       ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
			(read_write & 0x01) : 0),
		       SMBHSTADD(priv));
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		if (read_write == I2C_SMBUS_READ) {
			/* NB: page 240 of ICH5 datasheet also shows
			 * that DATA1 is the cmd field when reading */
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			outb_p(command, SMBHSTDAT1(priv));
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		} else
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			outb_p(command, SMBHSTCMD(priv));
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		block = 1;
		break;
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	case I2C_SMBUS_BLOCK_PROC_CALL:
		/*
		 * Bit 0 of the slave address register always indicate a write
		 * command.
		 */
		outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
		outb_p(command, SMBHSTCMD(priv));
		block = 1;
		break;
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	default:
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		dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
			size);
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		ret = -EOPNOTSUPP;
		goto out;
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	}

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	if (hwpec)	/* enable/disable hardware PEC */
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		outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
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	else
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		outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
		       SMBAUXCTL(priv));
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	if (block)
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		ret = i801_block_transaction(priv, data, read_write, size,
					     hwpec);
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	else
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		ret = i801_transaction(priv, xact);
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	/* Some BIOSes don't like it when PEC is enabled at reboot or resume
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	   time, so we forcibly disable it after every transaction. Turn off
	   E32B for the same reason. */
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	if (hwpec || block)
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		outb_p(inb_p(SMBAUXCTL(priv)) &
		       ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
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	if (block)
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		goto out;
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	if (ret)
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		goto out;
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	if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
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		goto out;
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	switch (xact & 0x7f) {
	case I801_BYTE:	/* Result put in SMBHSTDAT0 */
	case I801_BYTE_DATA:
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		data->byte = inb_p(SMBHSTDAT0(priv));
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		break;
	case I801_WORD_DATA:
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		data->word = inb_p(SMBHSTDAT0(priv)) +
			     (inb_p(SMBHSTDAT1(priv)) << 8);
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		break;
	}
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out:
	pm_runtime_mark_last_busy(&priv->pci_dev->dev);
	pm_runtime_put_autosuspend(&priv->pci_dev->dev);
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	mutex_unlock(&priv->acpi_lock);
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	return ret;
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}


static u32 i801_func(struct i2c_adapter *adapter)
{
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	struct i801_priv *priv = i2c_get_adapdata(adapter);

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	return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
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	       I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
	       I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
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	       ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
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	       ((priv->features & FEATURE_BLOCK_PROC) ?
		I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
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	       ((priv->features & FEATURE_I2C_BLOCK_READ) ?
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