Commit e83eb028 authored by Scott Wood's avatar Scott Wood
Browse files

powerpc/fsl: Add fsl,portid-mapping to corenet1-cf chips



Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
Cc: Diana Craciun <diana.craciun@freescale.com>
parent 8cb59788
......@@ -262,6 +262,7 @@ iommu@20000 {
interrupts = <
24 2 0 0
16 2 1 30>;
fsl,portid-mapping = <0x0f000000>;
pamu0: pamu@0 {
reg = <0 0x1000>;
......
......@@ -83,6 +83,7 @@ cpu0: PowerPC,e500mc@0 {
reg = <0>;
clocks = <&mux0>;
next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -92,6 +93,7 @@ cpu1: PowerPC,e500mc@1 {
reg = <1>;
clocks = <&mux1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -101,6 +103,7 @@ cpu2: PowerPC,e500mc@2 {
reg = <2>;
clocks = <&mux2>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x20000000>;
L2_2: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -110,6 +113,7 @@ cpu3: PowerPC,e500mc@3 {
reg = <3>;
clocks = <&mux3>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x10000000>;
L2_3: l2-cache {
next-level-cache = <&cpc>;
};
......
......@@ -289,6 +289,7 @@ iommu@20000 {
interrupts = <
24 2 0 0
16 2 1 30>;
fsl,portid-mapping = <0x0f000000>;
pamu0: pamu@0 {
reg = <0 0x1000>;
......
......@@ -84,6 +84,7 @@ cpu0: PowerPC,e500mc@0 {
reg = <0>;
clocks = <&mux0>;
next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -93,6 +94,7 @@ cpu1: PowerPC,e500mc@1 {
reg = <1>;
clocks = <&mux1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -102,6 +104,7 @@ cpu2: PowerPC,e500mc@2 {
reg = <2>;
clocks = <&mux2>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x20000000>;
L2_2: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -111,6 +114,7 @@ cpu3: PowerPC,e500mc@3 {
reg = <3>;
clocks = <&mux3>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x10000000>;
L2_3: l2-cache {
next-level-cache = <&cpc>;
};
......
......@@ -297,6 +297,7 @@ iommu@20000 {
interrupts = <
24 2 0 0
16 2 1 30>;
fsl,portid-mapping = <0x00f80000>;
pamu0: pamu@0 {
reg = <0 0x1000>;
......
......@@ -83,6 +83,7 @@ cpu0: PowerPC,e500mc@0 {
reg = <0>;
clocks = <&mux0>;
next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -92,6 +93,7 @@ cpu1: PowerPC,e500mc@1 {
reg = <1>;
clocks = <&mux1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -101,6 +103,7 @@ cpu2: PowerPC,e500mc@2 {
reg = <2>;
clocks = <&mux2>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x20000000>;
L2_2: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -110,6 +113,7 @@ cpu3: PowerPC,e500mc@3 {
reg = <3>;
clocks = <&mux3>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x10000000>;
L2_3: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -119,6 +123,7 @@ cpu4: PowerPC,e500mc@4 {
reg = <4>;
clocks = <&mux4>;
next-level-cache = <&L2_4>;
fsl,portid-mapping = <0x08000000>;
L2_4: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -128,6 +133,7 @@ cpu5: PowerPC,e500mc@5 {
reg = <5>;
clocks = <&mux5>;
next-level-cache = <&L2_5>;
fsl,portid-mapping = <0x04000000>;
L2_5: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -137,6 +143,7 @@ cpu6: PowerPC,e500mc@6 {
reg = <6>;
clocks = <&mux6>;
next-level-cache = <&L2_6>;
fsl,portid-mapping = <0x02000000>;
L2_6: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -146,6 +153,7 @@ cpu7: PowerPC,e500mc@7 {
reg = <7>;
clocks = <&mux7>;
next-level-cache = <&L2_7>;
fsl,portid-mapping = <0x01000000>;
L2_7: l2-cache {
next-level-cache = <&cpc>;
};
......
......@@ -294,6 +294,7 @@ iommu@20000 {
interrupts = <
24 2 0 0
16 2 1 30>;
fsl,portid-mapping = <0x3c000000>;
pamu0: pamu@0 {
reg = <0 0x1000>;
......
......@@ -90,6 +90,7 @@ cpu0: PowerPC,e5500@0 {
reg = <0>;
clocks = <&mux0>;
next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -99,6 +100,7 @@ cpu1: PowerPC,e5500@1 {
reg = <1>;
clocks = <&mux1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
};
......
......@@ -248,6 +248,7 @@ iommu@20000 {
#size-cells = <1>;
interrupts = <24 2 0 0
16 2 1 30>;
fsl,portid-mapping = <0x0f800000>;
pamu0: pamu@0 {
reg = <0 0x1000>;
......
......@@ -83,6 +83,7 @@ cpu0: PowerPC,e5500@0 {
reg = <0>;
clocks = <&mux0>;
next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -92,6 +93,7 @@ cpu1: PowerPC,e5500@1 {
reg = <1>;
clocks = <&mux1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -101,6 +103,7 @@ cpu2: PowerPC,e5500@2 {
reg = <2>;
clocks = <&mux2>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x20000000>;
L2_2: l2-cache {
next-level-cache = <&cpc>;
};
......@@ -110,6 +113,7 @@ cpu3: PowerPC,e5500@3 {
reg = <3>;
clocks = <&mux3>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x10000000>;
L2_3: l2-cache {
next-level-cache = <&cpc>;
};
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment