1. 27 May, 2021 1 commit
  2. 14 Apr, 2021 2 commits
  3. 22 Jul, 2020 2 commits
    • Raviteja Narayanam's avatar
      i2c: cadence: Clear HOLD bit at correct time in Rx path · 12d4d9ec
      Raviteja Narayanam authored
      
      
      There are few issues on Zynq SOC observed in the stress tests causing
      timeout errors. Even though all the data is received, timeout error
      is thrown. This is due to an IP bug in which the COMP bit in ISR is
      not set at end of transfer and completion interrupt is not generated.
      
      This bug is seen on Zynq platforms when the following condition occurs:
      Master read & HOLD bit set & Transfer size register reaches '0'.
      
      One workaround is to clear the HOLD bit before the transfer size
      register reaches '0'. The current implementation checks for this at
      the start of the loop and also only for less than FIFO DEPTH case
      (ignoring the equal to case).
      
      So clear the HOLD bit when the data yet to receive is less than or
      equal to the FIFO DEPTH. This avoids the IP bug condition.
      Signed-off-by: default avatarRaviteja Narayanam <raviteja.narayanam@xilinx.com>
      Acked-by: default avatarMichal Simek <michal.simek@xilinx.com>
      Signed-off-by: default avatarWolfram Sang <wsa@kernel.org>
      12d4d9ec
    • Raviteja Narayanam's avatar
      Revert "i2c: cadence: Fix the hold bit setting" · 0db9254d
      Raviteja Narayanam authored
      This reverts commit d358def7
      
      .
      
      There are two issues with "i2c: cadence: Fix the hold bit setting" commit.
      
      1. In case of combined message request from user space, when the HOLD
      bit is cleared in cdns_i2c_mrecv function, a STOP condition is sent
      on the bus even before the last message is started. This is because when
      the HOLD bit is cleared, the FIFOS are empty and there is no pending
      transfer. The STOP condition should occur only after the last message
      is completed.
      
      2. The code added by the commit is redundant. Driver is handling the
      setting/clearing of HOLD bit in right way before the commit.
      
      The setting of HOLD bit based on 'bus_hold_flag' is taken care in
      cdns_i2c_master_xfer function even before cdns_i2c_msend/cdns_i2c_recv
      functions.
      
      The clearing of HOLD bit is taken care at the end of cdns_i2c_msend and
      cdns_i2c_recv functions based on bus_hold_flag and byte count.
      Since clearing of HOLD bit is done after the slave address is written to
      the register (writing to address register triggers the message transfer),
      it is ensured that STOP condition occurs at the right time after
      completion of the pending transfer (last message).
      Signed-off-by: default avatarRaviteja Narayanam <raviteja.narayanam@xilinx.com>
      Acked-by: default avatarMichal Simek <michal.simek@xilinx.com>
      Signed-off-by: default avatarWolfram Sang <wsa@kernel.org>
      0db9254d
  4. 15 Apr, 2020 2 commits
  5. 24 Mar, 2020 1 commit
  6. 30 Jan, 2020 4 commits
  7. 30 May, 2019 1 commit
  8. 15 Feb, 2019 1 commit
  9. 31 Jul, 2017 1 commit
  10. 23 Jun, 2017 1 commit
  11. 25 Jan, 2017 1 commit
  12. 08 Sep, 2016 1 commit
  13. 22 Aug, 2016 1 commit
  14. 12 Mar, 2016 1 commit
    • Shubhrajyoti Datta's avatar
      i2c: cadence: Fix the kernel-doc warnings · 30e31a1f
      Shubhrajyoti Datta authored
      
      
      This fixes the below warnings
      drivers/i2c/busses/i2c-cadence.c:164: warning: No description found for parameter 'dev'
      drivers/i2c/busses/i2c-cadence.c:826: warning: No description found for parameter 'dev'
      drivers/i2c/busses/i2c-cadence.c:826: warning: Excess function parameter '_dev' description in 'cdns_i2c_runtime_suspend'
      drivers/i2c/busses/i2c-cadence.c:844: warning: No description found for parameter 'dev'
      drivers/i2c/busses/i2c-cadence.c:844: warning: Excess function parameter '_dev' description in 'cdns_i2c_runtime_resume'
      
      while at it also update the cdns_i2c_clear_bus_hold
      and the runtime function update.
      Tested-by: default avatarMichal Simek <michal.simek@xilinx.com>
      Signed-off-by: default avatarShubhrajyoti Datta <shubhraj@xilinx.com>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      30e31a1f
  15. 30 Nov, 2015 2 commits
  16. 10 Aug, 2015 2 commits
  17. 15 Mar, 2015 1 commit
  18. 14 Jan, 2015 1 commit
  19. 13 Jan, 2015 1 commit
    • Harini Katakam's avatar
      i2c: cadence: Handle > 252 byte transfers · 9fae82e1
      Harini Katakam authored
      
      
      The I2C controller sends a NACK to the slave when transfer size register
      reaches zero, irrespective of the hold bit. So, in order to handle transfers
      greater than 252 bytes, the transfer size register has to be maintained at a
      value >= 1. This patch implements the same.
      The interrupt status is cleared at the beginning of the isr instead of
      the end, to avoid missing any interrupts.
      Signed-off-by: default avatarHarini Katakam <harinik@xilinx.com>
      [wsa: added braces around else branch]
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      9fae82e1
  20. 04 Dec, 2014 1 commit
  21. 20 Oct, 2014 1 commit
  22. 06 Apr, 2014 1 commit