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Commit d1d94b01 authored by Marek Vasut's avatar Marek Vasut Committed by Dave Airlie
Browse files

drm/nouveau/fifo: Reinstate the correct engine bit programming

Commit 64f7c698 ("drm/nouveau/fifo: add engine_id hook") replaced
fifo/chang84.c g84_fifo_chan_engine() call with an indirect call of
fifo/g84.c g84_fifo_engine_id(). The G84_FIFO_ENGN_* values returned
from the later g84_fifo_engine_id() are incremented by 1 compared to
the previous g84_fifo_chan_engine() return values.

This is fine either way for most of the code, except this one line
where an engine bit programmed into the hardware is derived from the
return value. Decrement the return value accordingly, otherwise the
wrong engine bit is programmed into the hardware and that leads to
the following failure:
nouveau 0000:01:00.0: gr: 00000030 [ILLEGAL_MTHD ILLEGAL_CLASS] ch 1 [003fbce000 DRM] subc 3 class 0000 mthd 085c data 00000420

On the following hardware:
lspci -s 01:00.0
01:00.0 VGA compatible controller: NVIDIA Corporation GT216GLM [Quadro FX 880M] (rev a2)
lspci -ns 01:00.0
01:00.0 0300: 10de:0a3c (rev a2)

Fixes: 64f7c698

 ("drm/nouveau/fifo: add engine_id hook")
Signed-off-by: default avatarMarek Vasut <>
Cc: <> # 5.12+
Cc: Ben Skeggs <>
Cc: Karol Herbst <>
Cc: Lyude Paul <>
Reviewed-by: default avatarKarol Herbst <>
Reviewed-by: default avatarBen Skeggs <>
Signed-off-by: default avatarKarol Herbst <>

Signed-off-by: default avatarDave Airlie <>
parent b253c302
......@@ -82,7 +82,7 @@ g84_fifo_chan_engine_fini(struct nvkm_fifo_chan *base,
if (offset < 0)
return 0;
engn = fifo->base.func->engine_id(&fifo->base, engine);
engn = fifo->base.func->engine_id(&fifo->base, engine) - 1;
save = nvkm_mask(device, 0x002520, 0x0000003f, 1 << engn);
nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12);
done = nvkm_msec(device, 2000,
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