- 19 Dec, 2016 18 commits
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Andrew Jones authored
Reviewed-by:
Eric Auger <eric.auger@redhat.com> Signed-off-by:
Andrew Jones <drjones@redhat.com>
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Andrew Jones authored
Add some gicv2 support. This just adds init and enable functions, allowing unit tests to start messing with it. Reviewed-by:
Andre Przywara <andre.przywara@arm.com> Reviewed-by:
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Andrew Jones authored
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Alex Bennée <alex.bennee@linaro.org> Reviewed-by:
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Andrew Jones authored
Allow a thread to wait some specified amount of time. Can specify in cycles, usecs, and msecs. Reviewed-by:
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Andrew Jones authored
By adding support for launching with gicv3 we can break the 8 vcpu limit. This patch adds support to smp code and also selects the vgic model corresponding to the host. The vgic model may also be manually selected by adding e.g. -machine gic-version=3 to extra_params. Reviewed-by:
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Andrew Jones authored
In many tests one or more cpus wait for events from other cpus. However, with TCG, if the event triggering cpus then continue without first informing TCG it should schedule other cpus, then those other cpus may never get scheduled, and never see their events. This is because the TCG scheduler relies on either the currently running cpu to invoke an instruction that results in scheduling or for some I/O event to occur, and then to do scheduling while handling the I/O. kvm-unit-tests do not have external I/O events, so we must invoke a yielding instruction wherever needed. cpu_relax() is almost always a place it's needed. While this change is mostly for TCG, it's fine to do for KVM as well. The Linux kernel made the same change with 1baa82f4803 for armv8. As the yield instruction is also available on armv7, we make the change for both. Signed-off-by: -
Andrew Jones authored
The TCG PMU is barely implemented for ARM and not at all implemented for AArch64. Let's not bother running the TCG-only tests yet. We'll likely move them to a new TCG-only unittests.cfg at some point before re-enabling them too. Signed-off-by: -
Andrew Jones authored
The spec for ID_DFR0_EL1 says "In an AArch64-only implementation, this register is UNKNOWN." Indeed ThunderX just returns zero when that register is read. This means we can't rely on a non-zero value to determine if we can test the PMU. For AArch64 we need to read ID_AA64DFR0_EL1. This patch has the side effect of no longer running PMU tests on TCG for AArch64. That's actually another fix, though, as TCG chooses not to implement a PMU for AArch64 at this time. The only way it worked before was probing the wrong register and proceeding even though the version was 2, which is not a valid version for AArch64. When TCG eventually implements a PMU things should "just work". Reviewed-by:
Wei Huang <wei@redhat.com> Signed-off-by:
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Calculate the numbers of cycles per instruction (CPI) implied by ARM PMU cycle counter values. The code includes a strict checking facility intended for the -icount option in TCG mode in the configuration file. Signed-off-by:
Christopher Covington <cov@codeaurora.org> Signed-off-by:
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Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, even for the smallest delta of two subsequent reads. Signed-off-by:
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Beginning with a simple sanity check of the control register, add a unit test for the ARM Performance Monitors Unit (PMU). Signed-off-by:
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This patch adds two new macros to support read/write operations of ARMv7 and ARMv8 system registers. As part of the change, xstr() is revised to support variable arguments. With it, ARMv7 system register can be defined with __ACCESS_CP15() or __ACCESS_CP15_64() depending if it is 32-bit or 64-bit. get_mpidr() is re-written with new macros. Suggested-by:
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To prepare for future support of ARMv8 system register, rename cp15.h file to sysreg.h, with _ASMARM_CP15_H_ renamed to _ASMARM_SYSREG_H_ in header file. Signed-off-by:
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As distro compilers move towards defaults for build hardening for things like ASLR we need to force -fno-pic. Failure to do can lead to weird relocation problems when we build our "lat" binaries. Signed-off-by:
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Failing to translate the PCI address obtained from the bar means something isn't right with the PCI setup. As this should never happen, assert when it does. Cc: Thomas Huth <thuth@redhat.com> Cc: Andrew Jones <drjones@redhat.com> Signed-off-by:
Alexander Gordeev <agordeev@redhat.com> [Added commit message] Signed-off-by:
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Function pci_host_bridge_get_paddr() returns zero in case no mapping for a passed PCI address is found. All ones is a better choice, since zero may be a legitimate physical address. Suggested-by:
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PCI I/O and Memory must be allocated to a device in a naturally aligned way. For example, if a device asks for 0xB0 of PCI I/O space then it must be aligned on an address that is a multiple of 0xB0 (http://www.tldp.org/LDP/tlk/dd/pci.html ) Cc: Thomas Huth <thuth@redhat.com> Cc: Andrew Jones <drjones@redhat.com> Reported-by:
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Size of a BAR is naturally aligned so there is no need to align it explicitly. Cc: Thomas Huth <thuth@redhat.com> Cc: Andrew Jones <drjones@redhat.com> Signed-off-by:
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- 16 Dec, 2016 1 commit
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Jim Mattson authored
Int3 (#BP) and INTO (#OF) are unusual, in that they are reported as "software exception" rather than "hardware exception" in the VM-exit interruption information field of the VMCS. Signed-off-by:
Jim Mattson <jmattson@google.com> Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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- 30 Nov, 2016 1 commit
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Kyle Huey authored
This test checks that single stepping through CPUID and RDMSR works. Both instructions trigger VM exits and are emulated by the hypervisor. Signed-off-by:
Kyle Huey <khuey@kylehuey.com> [Fixed dr6 indices to check even dr6[5] and dr6[6].] Signed-off-by:
Radim Krčmář <rkrcmar@redhat.com>
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- 22 Nov, 2016 2 commits
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Andrew Jones authored
Test writers sometimes want to output informational messages, but they don't want to use printf because they want the prefixes as well. Rather than creating "fake" tests that always pass, with report(fmt, true, ...), provide report_info(fmt, ...). This generates 'INFO: prefixes...: message' Signed-off-by:
Thomas Huth <thuth@redhat.com> Signed-off-by:
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Andrew Jones authored
Signed-off-by:
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- 21 Nov, 2016 3 commits
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Jim Mattson authored
This test disables and re-enables the local APIC and ensures that CPUID.1H:EDX.APIC[bit 9] mirrors IA32_APIC_BASE[11]. Signed-off-by:
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Andrew Jones authored
Adding pci-test to arm allowed us to see that a virtio-net-pci device was getting added to our machine by default. Unit tests should configure the most minimal machines they can, only adding devices necessary for the tests. Let's add -nodefaults to all the run scripts. I tested all arches (powerpc and arm on tcg). There were no unexpected changes. Signed-off-by:
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Andrew Jones authored
Add two changes to run_qemu. The first saves/restores terminal settings. This solves an annoying loss of terminal echo when QEMU aborts during a test run. The second ensures we see a message about the abort, because the "Aborted (core dumped)" message we should see gets eaten. We also add a message to run()'s failure cases in its exit code processing to handle signals in general. Note, the first change is necessary because QEMU modifies the terminal settings when using '-serial stdio', but calling abort() invokes exit without first calling qemu_chr_free(serial_hds[0]) to restore them. (Additionally we fixup the premature failure check to only capture the last line, like it says it's doing.) Reported-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
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- 15 Nov, 2016 1 commit
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Radim Krčmář authored
Not doing so hid stderr output when the test was stuck and subsequently killed with ^C. Signed-off-by:
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- 08 Nov, 2016 13 commits
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Alexander Gordeev authored
Suggested-by:
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Alexander Gordeev authored
Cc: Thomas Huth <thuth@redhat.com> Cc: Andrew Jones <drjones@redhat.com> Cc: Peter Xu <peterx@redhat.com> Reviewed-by:
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Alexander Gordeev authored
Unlike x86, other architectures using generic ECAM PCI host do not have a luxury of PCI bus initialized by a BIOS and ready to use at start. Thus, we need allocate and assign resources to all devices, much like an architecture's firmware would do. There is no any sort of resource management for memory and io spaces, since only ones-per-BAR allocations are expected and no deallocations at all. Cc: Thomas Huth <thuth@redhat.com> Cc: Andrew Jones <drjones@redhat.com> Cc: Peter Xu <peterx@redhat.com> Suggested-by:
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Alexander Gordeev authored
Cc: Thomas Huth <thuth@redhat.com> Cc: Andrew Jones <drjones@redhat.com> Cc: Peter Xu <peterx@redhat.com> Suggested-by:
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Alexander Gordeev authored
Cc: Thomas Huth <thuth@redhat.com> Cc: Andrew Jones <drjones@redhat.com> Cc: Peter Xu <peterx@redhat.com> Reviewed-by:
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Alexander Gordeev authored
Because the counterpart to pci_bar_set_addr() setter is pci_bar_addr() getter, these names become inconsistent. Rename pci_bar_addr() to pci_bar_get_addr() also to make the resulting names conform to each other. Cc: Thomas Huth <thuth@redhat.com> Cc: Andrew Jones <drjones@redhat.com> Cc: Peter Xu <peterx@redhat.com> Reviewed-by:
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Alexander Gordeev authored
This update makes pci_bar_addr() interface 64 bit BARs aware and introduces a concept of PCI address translation. An architecutre should implement pci_translate_addr() interface in order to provide mapping between PCI bus address and CPU physical address. Cc: Thomas Huth <thuth@redhat.com> Cc: Andrew Jones <drjones@redhat.com> Cc: Peter Xu <peterx@redhat.com> Reviewed-by:
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Alexander Gordeev authored
Cc: Thomas Huth <thuth@redhat.com> Cc: Andrew Jones <drjones@redhat.com> Cc: Peter Xu <peterx@redhat.com> Reviewed-by:
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Alexander Gordeev authored
Cc: Thomas Huth <thuth@redhat.com> Cc: Andrew Jones <drjones@redhat.com> Cc: Peter Xu <peterx@redhat.com> Reviewed-by:
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Alexander Gordeev authored
Cc: Thomas Huth <thuth@redhat.com> Cc: Andrew Jones <drjones@redhat.com> Cc: Peter Xu <peterx@redhat.com> Reviewed-by:
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Alexander Gordeev authored
Cc: Thomas Huth <thuth@redhat.com> Cc: Andrew Jones <drjones@redhat.com> Cc: Peter Xu <peterx@redhat.com> Reviewed-by:
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Alexander Gordeev authored
Cc: Thomas Huth <thuth@redhat.com> Cc: Andrew Jones <drjones@redhat.com> Cc: Peter Xu <peterx@redhat.com> Reviewed-by:
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Andrew Jones authored
Signed-off-by:
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- 03 Nov, 2016 1 commit
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Paolo Bonzini authored
Signed-off-by:
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