- 21 Jan, 2020 2 commits
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Wainer dos Santos Moschetta authored
The 'Guarding unsafe tests' section mention the unittests.cfg file which was never introduced before. In this change it was added a section with a few words about the tests configuration file (unittests.cfg). Signed-off-by:
Wainer dos Santos Moschetta <wainersm@redhat.com> Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Wainer dos Santos Moschetta authored
There are formatting issues that prevent README.md from being rendered correctly in a browser. This patch fixes the following categories of issues: - blocks which aren't indented correctly; - texts wrapped in <> which need escape, or be replaced with another thing. Also some inline commands are marked with ``. Signed-off-by:
Andrew Jones <drjones@redhat.com> Signed-off-by:
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- 19 Jan, 2020 1 commit
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Krish Sadhukhan authored
According to section "Checks on Guest Control Registers, Debug Registers, and and MSRs" in Intel SDM vol 3C, the following checks are performed on vmentry of nested guests: If the "load debug controls" VM-entry control is 1, - bits 63:32 in the DR7 field must be 0. Signed-off-by:Krish Sadhukhan <krish.sadhukhan@oracle.com> Reviewed-by:
Karl Heubaum <karl.heubaum@oracle.com> Co-developed-by:
Jim Mattson <jmattson@google.com> Signed-off-by:
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- 18 Jan, 2020 4 commits
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Babu Moger authored
vmware_backdoors test fails if the kvm module parameter enable_vmware_backdoor is not set to Y. Add a check before running the test. Suggested-by:
Wei Huang <Wei.Huang2@amd.com> Signed-off-by:
Babu Moger <babu.moger@amd.com> Reviewed-by:
Liran Alon <liran.alon@oracle.com> Signed-off-by:
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Alex Bennée authored
This is a editor agnostic configuration file to specify the indentation style for the project. It is supported by both Emacs and Vim as well as some other inconsequential editors. Signed-off-by:
Alex Bennée <alex.bennee@linaro.org> Signed-off-by:
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Nadav Amit authored
Now that comprehensive search for maximum VMCS field index is performed, the tracking of the maximum index in __check_vmcs_field() is no longer needed. Remove all the related logic accordingly. Cc: Jim Mattson <jmattson@google.com> Cc: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by:
Nadav Amit <namit@vmware.com> Signed-off-by:
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Nadav Amit authored
Search all VMCS fields when looking for the max VMCS field index. Perform the search backwards to save some time. Change the existing test to compare the maximum expected index (based on MSRs) is equal to the actual one. This improves the test that currently performs greater-equal comparison. Suggested-by:
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- 08 Jan, 2020 1 commit
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- 07 Jan, 2020 4 commits
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Thomas Huth authored
Add an entry for this test to the unittests.cfg file and enable it in the CI pipelines. Signed-off-by:
Thomas Huth <thuth@redhat.com> Signed-off-by:
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Thomas Huth authored
Use a proper report() in the test instead of printf(), and add it to the unittests.cfg and the CI yaml files. Signed-off-by:
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Thomas Huth authored
No functional change, just use tabs for indentation. Signed-off-by:
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Thomas Huth authored
QEMU recently changed its output if it could not open a kernel file from "could not load kernel ..." to "could not open kernel ...", see QEMU commit 350f5233d755 ("hw/i386/pc: avoid an assignment in if condition in x86_load_linux()"). Thus we have to adapt our script that looks for this string accordingly. Signed-off-by:
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- 06 Jan, 2020 13 commits
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According to the ARM ARM [1]: "In Armv8, any permitted instruction cache implementation can be described as implementing the IVIPT Extension to the Arm architecture. The formal definition of the Arm IVIPT Extension is that it reduces the instruction cache maintenance requirement to the following condition: Instruction cache maintenance is required only after writing new data to a PA that holds an instruction". We never patch instructions in the boot path, so remove the icache invalidation from asm_mmu_enable. Tests that modify instructions (like the cache test) should have their own icache maintenance operations. [1] ARM DDI 0487E.a, section D5.11.2 "Instruction caches" Signed-off-by:
Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by:
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Let's invalidate the TLB before enabling the MMU, not after, so we don't accidently use a stale TLB mapping. For arm, we add a TLBIALL operation, which applies only to the PE that executed the instruction [1]. For arm64, we already do that in asm_mmu_enable. We now find ourselves in a situation where we issue an extra invalidation after asm_mmu_enable returns. Remove this redundant call to tlb_flush_all. [1] ARM DDI 0406C.d, section B3.10.6 Reviewed-by:
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There's really no need to invalidate the TLB entries for all CPUs when enabling the MMU for the current CPU, so use the non-shareable version of the TLBI operation (and downgrade the DSB accordingly). Signed-off-by:
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When the MMU is off, all addresses are physical addresses. If the stack pointer is not an identity mapped address (the virtual address is not the same as the physical address), then we end up trying to access an invalid memory region. This can happen if we call mmu_disable from a secondary CPU, which has its stack allocated from the vmalloc region. Reviewed-by:
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According the Generic Interrupt Controller versions 2, 3 and 4 architecture specifications, a write of 0 to the GIC{D,R}_ISENABLER{,0} registers is ignored; this is also how KVM emulates the corresponding register. Write instead to the ICENABLER register when disabling the timer interrupt. Note that fortunately for us, the timer test was still working as intended because KVM does the sensible thing and all interrupts are disabled by default when creating a VM. Signed-off-by:Andre Przywara <andre.przywara@arm.com> Signed-off-by:
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kvm-unit-tests uses block mappings, so let's expand the mmu_clear_user function to handle those as well. Now that the function knows about block mappings, we cannot simply assume that if an address isn't mapped we can map it as a regular page. Change the semantics of the function to fail quite loudly if the address isn't mapped, and shift the burden on the caller to map the address as a page or block mapping before calling mmu_clear_user. Also make mmu_clear_user more flexible by adding a pgtable parameter, instead of assuming that the change always applies to the current translation tables. Signed-off-by:
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flush_tlb_all performs a TLBIALL, which invalidates the entire TLB and affects only the executing PE; translation table walks are now Inner Shareable, so execute a TLBIALLIS (invalidate TLB Inner Shareable) instead. TLBIALLIS is the equivalent of TLBIALL [1] when the multiprocessing extensions are implemented, which are mandated by the virtualization extensions. Also add the necessary barriers to tlb_flush_all and a comment to flush_dcache_addr stating what instruction is uses (unsurprisingly, it's DCCIMVAC, which does a dcache clean and invalidate by VA to PoC). [1] ARM DDI 0406C.d, section B3.10.6 Signed-off-by:
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pgtable.h is used only by mmu.c, where it is included after alloc_page.h. Reviewed-by:
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The first version of PSCI required an argument for CPU_OFF, the power_state argument, which was removed in version 0.2 of the specification [1]. kvm-unit-tests supports PSCI 0.2, and KVM ignores any CPU_OFF parameters, so let's remove the PSCI_POWER_STATE_TYPE_POWER_DOWN parameter. [1] ARM DEN 0022D, section 7.3. Signed-off-by:
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Use WRITE_ONCE to prevent store tearing when updating an entry in the translation tables. Without WRITE_ONCE, the compiler, even though it is unlikely, can emit several stores when changing the table, and we might end up with bogus TLB entries. It's worth noting that the existing code is mostly fine without any changes because the translation tables are updated in one of the following situations: - When the tables are being created with the MMU off, which means no TLB caching is being performed. - When new page table entries are added as a result of vmalloc'ing a stack for a secondary CPU, which doesn't happen very often. - When clearing the PTE_USER bit for the cache test, and store tearing has no effect on the table walker because there are no intermediate values between bit values 0 and 1. We still use WRITE_ONCE in this case for consistency. However, the functions are global and there is nothing preventing someone from writing a test that uses them in a different scenario. Let's make sure that when that happens, there will be no breakage once in a blue moon. Reported-by:
Mark Rutland <mark.rutland@arm.com> Signed-off-by:
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Add the WRITE_ONCE and READ_ONCE macros which are used to prevent the compiler from optimizing a store or a load, respectively, into something else. Cc: Drew Jones <drjones@redhat.com> Cc: Laurent Vivier <lvivier@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Cc: David Hildenbrand <david@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by:
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We need to issue a DSB before doing TLB invalidation to make sure that the table walker sees the new VA mapping after the TLBI finishes. For flush_tlb_page, we do a DSB ISHST (synchronization barrier for writes in the Inner Shareable domain) because translation table walks are now coherent for arm. For local_flush_tlb_all, we only need to affect the Non-shareable domain, and we do a DSB NSHST. We need a synchronization barrier here, and not a memory ordering barrier, because a table walk is not a memory operation and therefore not affected by the DMB. For the same reasons, we downgrade the full system DSB after the TLBI to a DSB ISH (synchronization barrier for reads and writes in the Inner Shareable domain), and, respectively, DSB NSH (in the Non-shareable domain). With these two changes, our TLB maintenance functions now match what Linux does in __flush_tlb_kernel_page, and, respectively, in local_flush_tlb_all. A similar change was implemented in Linux commit 62cbbc42e001 ("ARM: tlb: reduce scope of barrier domains for TLB invalidation"). Signed-off-by: -
On ARMv7 with multiprocessing extensions (which are mandated by the virtualization extensions [1]), and on ARMv8, translation table walks are coherent [2, 3], which means that no dcache maintenance operations are required when changing the tables. Remove the maintenance operations so that we do only the minimum required to ensure correctness. Translation table walks are coherent if the memory where the tables themselves reside have the same shareability and cacheability attributes as the translation table walks. For ARMv8, this is already the case, and it is only a matter of removing the cache operations. However, for ARMv7, translation table walks were being configured as Non-shareable (TTBCR.SH0 = 0b00) and Non-cacheable (TTBCR.{I,O}RGN0 = 0b00). Fix that by marking them as Inner Shareable, Normal memory, Inner and Outer Write-Back Write-Allocate Cacheable. Because translation table walks are now coherent on arm, replace the TLBIMVAA operation with TLBIMVAAIS in flush_tlb_page, which acts on the Inner Shareable domain instead of being private to the PE. The functions that update the translation table are called when the MMU is off, or to modify permissions, in the case of the cache test, so break-before-make is not necessary. [1] ARM DDI 0406C.d, section B1.7 [2] ARM DDI 0406C.d, section B3.3.1 [3] ARM DDI 0487E.a, section D13.2.72 [4] ARM DDI 0487E.a, section K11.5.3 Reported-by:
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- 27 Dec, 2019 4 commits
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If the /cpus node contains nodes other than /cpus/cpu*, for example: /cpus/cpu-map/. The test will issue an unexpected assert error as follow: [root@localhost]# ./arm-run arm/spinlock-test.flat qemu-system-aarch64 -nodefaults -machine virt,gic-version=host,accel=kvm -cpu host -device virtio-serial-device -device virtconsole,chardev=ctd -chardev testdev,id=ctd -device pci-testdev -display none -serial stdio -kernel arm/spinlock-test.flat # -initrd /tmp/tmp.mwPLiF4EWm lib/arm/setup.c:64: assert failed: ret == 0 STACK: In this patch, ignore the non-cpu subnodes instead of return an error. Signed-off-by:Zeng Tao <prime.zeng@hisilicon.com> Signed-off-by:
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Andrew Jones authored
Since QEMU commit 83ad95957c7e ("pl031: Expose RTCICR as proper WC register") the PL031 test gets into an infinite loop. Now we must write bit zero of RTCICR to clear the IRQ status. Before, writing anything to RTCICR would work. As '1' is a member of 'anything' writing it should work for old QEMU as well. Cc: Alexander Graf <graf@amazon.com> Signed-off-by:Alexander Graf <graf@amazon.com>
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Andrew Jones authored
Variable argument macros frequently depend on floating point registers. Indeed we needed to enable the VFP for arm64 since its introduction in order to use printf and the like. Somehow we didn't need to do that for arm32 until recently when compiling with GCC 9. Tested-by:
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pl031 and spinlock testcase without prefix, when running the unit tests in TAP mode (./run_tests.sh -t), it is difficult to the test results. The test results： ok 13 - Periph/PCell IDs match ok 14 - R/O fields are R/O ok 15 - RTC ticks at 1HZ ok 16 - RTC IRQ not pending yet ... ok 24 - RTC IRQ not pending anymore ok 25 - CPU1: Done - Errors: 0 ok 26 - CPU0: Done - Errors: 0 It should be like this： ok 13 - pl031: Periph/PCell IDs match ok 14 - pl031: R/O fields are R/O ok 15 - pl031: RTC ticks at 1HZ ok 16 - pl031: RTC IRQ not pending yet ... ok 24 - pl031: RTC IRQ not pending anymore ok 25 - spinlock: CPU0: Done - Errors: 0 ok 26 - spinlock: CPU1: Done - Errors: 0 Signed-off-by:
Chen Qun <kuhn.chenqun@huawei.com> Signed-off-by:
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- 18 Dec, 2019 1 commit
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Peter Shier authored
The GNU assembler (gas) allows omitting operands where there is only a single choice e.g. "VMRUN rAX".The LLVM assembler requires those operands even though they are the default and only choice. In addition, LLVM does not allow a CLGI instruction with a terminating \n\t. Adding a ; separator after the instruction is a workaround. Signed-off-by:
Peter Shier <pshier@google.com> Reviewed-by:
Marc Orr <marcorr@google.com> Reviewed-by:
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- 10 Dec, 2019 6 commits
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Krish Sadhukhan authored
Signed-off-by:
Mark Kanda <mark.kanda@oracle.com> Reviewed-by:
David Hildenbrand <david@redhat.com> Signed-off-by:
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Paolo Bonzini authored
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Krish Sadhukhan authored
According to section "Checks on Guest Control Registers, Debug Registers, and and MSRs" in Intel SDM vol 3C, the following checks are performed on vmentry of nested guests: "The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field must each contain a canonical address." Signed-off-by: -
Krish Sadhukhan authored
..as the latter already does what the former does. Signed-off-by:
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Krish Sadhukhan authored
Signed-off-by:
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Cathy Avery authored
The test confirms the influence of the V_INTR_MASKING bit on RFLAGS.IF. The expectation is while running a guest with V_INTR_MASKING cleared to zero: - EFLAGS.IF controls both virtual and physical interrupts. While running a guest with V_INTR_MASKING set to 1: - The host EFLAGS.IF at the time of the VMRUN is saved and controls physical interrupts while the guest is running. - The guest value of EFLAGS.IF controls virtual interrupts only. As discussed previously, this patch also modifies the vmrun loop ( test_run ) to allow running with HIF=0 Signed-off-by:
Cathy Avery <cavery@redhat.com> Signed-off-by:
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- 09 Dec, 2019 1 commit
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Thomas Huth authored
KVM works on Travis in 32-bit, too, so we can enable more tests there. Signed-off-by:
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- 06 Dec, 2019 2 commits
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Thomas Huth authored
Commit c09c54c6 ("lib: use an argument which doesn't require default argument promotion") fixed a warning that occurs with Clang, but introduced a regression: If the "pass" parameter is a value which has only set the condition bits in the upper 32 bits of a 64 bit value, the condition is now false since the value is truncated to "unsigned int" so that the upper bits are simply discarded. We fixed it by reverting the commit, but that of course also means trouble with Clang again. We can not use "bool" if it is the last parameter before the variable argument list. The proper fix is to swap the parameters around and make the format string the last parameter. This patch (except the changes in lib/libcflat.h and lib/report.c and some rebase conflicts along the way) has basically been created with following coccinelle script (with some additional manual tweaking of long and disabled lines afterwards): @@ expression fmt; expression pass; expression list args; @@ report( -fmt, pass +pass, fmt , args); @@ expression fmt; expression pass; expression list args; @@ report_xfail( -fmt, xfail, pass +xfail, pass, fmt , args); Tested-by:
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Thomas Huth authored
Radim's mail address @redhat.com is not valid anymore, so we should remove this line from the MAINTAINERS file. Thanks for all your work on kvm-unit-tests during the past years, Radim! Signed-off-by:
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- 04 Dec, 2019 1 commit
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Aaron Lewis authored
Verify that the difference between a guest RDTSC instruction and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12's VM-exit MSR-store list is less than 750 cycles, 99.9% of the time. Testcase for Linux kernel commit 662f1d1d1931 ("KVM: nVMX: Add support for capturing highest observable L2 TSC”). Signed-off-by:Aaron Lewis <aaronlewis@google.com> Reviewed-by:
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