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The PCI Local Bus Specification, Rev. 3.0, Section 6.2.5.1. "Address Maps" states: "Devices that map control functions into I/O Space must not consume more than 256 bytes per I/O Base Address register." Yet all the PCI devices allocate IO ports of IOPORT_SIZE (= 1024 bytes). Fix this by having PCI devices use 256 bytes ports for IO BARs. There is no hard requirement on the size of the memory region described by memory BARs. However, the region must be big enough to hold the virtio common interface described in [1], which is 20 bytes, and other MSI-X and/or device specific configuration. To be consistent, let's also limit the memory region described by BAR1 to 256. This is the same size used by BAR2 for each of the two MSI-X vectors. [1] VIRTIO Version 1.0 Committee Specification 04, section 4.4.8. Signed-off-by: Julien Thierry <julien.thierry@arm.com> [Added rationale for changing BAR1 size to PCI_IO_SIZE] Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
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