intvec_32.S 52.3 KB
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/*
 * Copyright 2010 Tilera Corporation. All Rights Reserved.
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful, but
 *   WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *   NON INFRINGEMENT.  See the GNU General Public License for
 *   more details.
 *
 * Linux interrupt vectors.
 */

#include <linux/linkage.h>
#include <linux/errno.h>
#include <linux/init.h>
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#include <linux/unistd.h>
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#include <asm/ptrace.h>
#include <asm/thread_info.h>
#include <asm/irqflags.h>
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#include <asm/atomic_32.h>
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#include <asm/asm-offsets.h>
#include <hv/hypervisor.h>
#include <arch/abi.h>
#include <arch/interrupts.h>
#include <arch/spr_def.h>

#ifdef CONFIG_PREEMPT
# error "No support for kernel preemption currently"
#endif

#define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg)

#define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR)

#if !CHIP_HAS_WH64()
	/* By making this an empty macro, we can use wh64 in the code. */
	.macro  wh64 reg
	.endm
#endif

	.macro  push_reg reg, ptr=sp, delta=-4
	{
	 sw     \ptr, \reg
	 addli  \ptr, \ptr, \delta
	}
	.endm

	.macro  pop_reg reg, ptr=sp, delta=4
	{
	 lw     \reg, \ptr
	 addli  \ptr, \ptr, \delta
	}
	.endm

	.macro  pop_reg_zero reg, zreg, ptr=sp, delta=4
	{
	 move   \zreg, zero
	 lw     \reg, \ptr
	 addi   \ptr, \ptr, \delta
	}
	.endm

	.macro  push_extra_callee_saves reg
	PTREGS_PTR(\reg, PTREGS_OFFSET_REG(51))
	push_reg r51, \reg
	push_reg r50, \reg
	push_reg r49, \reg
	push_reg r48, \reg
	push_reg r47, \reg
	push_reg r46, \reg
	push_reg r45, \reg
	push_reg r44, \reg
	push_reg r43, \reg
	push_reg r42, \reg
	push_reg r41, \reg
	push_reg r40, \reg
	push_reg r39, \reg
	push_reg r38, \reg
	push_reg r37, \reg
	push_reg r36, \reg
	push_reg r35, \reg
	push_reg r34, \reg, PTREGS_OFFSET_BASE - PTREGS_OFFSET_REG(34)
	.endm

	.macro  panic str
	.pushsection .rodata, "a"
1:
	.asciz  "\str"
	.popsection
	{
	 moveli r0, lo16(1b)
	}
	{
	 auli   r0, r0, ha16(1b)
	 jal    panic
	}
	.endm

#ifdef __COLLECT_LINKER_FEEDBACK__
	.pushsection .text.intvec_feedback,"ax"
intvec_feedback:
	.popsection
#endif

	/*
	 * Default interrupt handler.
	 *
	 * vecnum is where we'll put this code.
	 * c_routine is the C routine we'll call.
	 *
	 * The C routine is passed two arguments:
	 * - A pointer to the pt_regs state.
	 * - The interrupt vector number.
	 *
	 * The "processing" argument specifies the code for processing
	 * the interrupt. Defaults to "handle_interrupt".
	 */
	.macro  int_hand vecnum, vecname, c_routine, processing=handle_interrupt
	.org    (\vecnum << 8)
intvec_\vecname:
	.ifc    \vecnum, INT_SWINT_1
	blz     TREG_SYSCALL_NR_NAME, sys_cmpxchg
	.endif

	/* Temporarily save a register so we have somewhere to work. */

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	mtspr   SPR_SYSTEM_SAVE_K_1, r0
	mfspr   r0, SPR_EX_CONTEXT_K_1
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	/* The cmpxchg code clears sp to force us to reset it here on fault. */
	{
	 bz     sp, 2f
	 andi   r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK  /* mask off ICS */
	}

	.ifc    \vecnum, INT_DOUBLE_FAULT
	/*
	 * For double-faults from user-space, fall through to the normal
	 * register save and stack setup path.  Otherwise, it's the
	 * hypervisor giving us one last chance to dump diagnostics, and we
	 * branch to the kernel_double_fault routine to do so.
	 */
	bz      r0, 1f
	j       _kernel_double_fault
1:
	.else
	/*
	 * If we're coming from user-space, then set sp to the top of
	 * the kernel stack.  Otherwise, assume sp is already valid.
	 */
	{
	 bnz    r0, 0f
	 move   r0, sp
	}
	.endif

	.ifc    \c_routine, do_page_fault
	/*
	 * The page_fault handler may be downcalled directly by the
	 * hypervisor even when Linux is running and has ICS set.
	 *
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	 * In this case the contents of EX_CONTEXT_K_1 reflect the
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	 * previous fault and can't be relied on to choose whether or
	 * not to reinitialize the stack pointer.  So we add a test
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	 * to see whether SYSTEM_SAVE_K_2 has the high bit set,
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	 * and if so we don't reinitialize sp, since we must be coming
	 * from Linux.  (In fact the precise case is !(val & ~1),
	 * but any Linux PC has to have the high bit set.)
	 *
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	 * Note that the hypervisor *always* sets SYSTEM_SAVE_K_2 for
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	 * any path that turns into a downcall to one of our TLB handlers.
	 */
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	mfspr   r0, SPR_SYSTEM_SAVE_K_2
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	{
	 blz    r0, 0f    /* high bit in S_S_1_2 is for a PC to use */
	 move   r0, sp
	}
	.endif

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	/*
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	 * SYSTEM_SAVE_K_0 holds the cpu number in the low bits, and
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	 * the current stack top in the higher bits.  So we recover
	 * our stack top by just masking off the low bits, then
	 * point sp at the top aligned address on the actual stack page.
	 */
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	mfspr   r0, SPR_SYSTEM_SAVE_K_0
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	mm      r0, r0, zero, LOG2_THREAD_SIZE, 31

0:
	/*
	 * Align the stack mod 64 so we can properly predict what
	 * cache lines we need to write-hint to reduce memory fetch
	 * latency as we enter the kernel.  The layout of memory is
	 * as follows, with cache line 0 at the lowest VA, and cache
	 * line 4 just below the r0 value this "andi" computes.
	 * Note that we never write to cache line 4, and we skip
	 * cache line 1 for syscalls.
	 *
	 *    cache line 4: ptregs padding (two words)
	 *    cache line 3: r46...lr, pc, ex1, faultnum, orig_r0, flags, pad
	 *    cache line 2: r30...r45
	 *    cache line 1: r14...r29
	 *    cache line 0: 2 x frame, r0..r13
	 */
	andi    r0, r0, -64

	/*
	 * Push the first four registers on the stack, so that we can set
	 * them to vector-unique values before we jump to the common code.
	 *
	 * Registers are pushed on the stack as a struct pt_regs,
	 * with the sp initially just above the struct, and when we're
	 * done, sp points to the base of the struct, minus
	 * C_ABI_SAVE_AREA_SIZE, so we can directly jal to C code.
	 *
	 * This routine saves just the first four registers, plus the
	 * stack context so we can do proper backtracing right away,
	 * and defers to handle_interrupt to save the rest.
	 * The backtracer needs pc, ex1, lr, sp, r52, and faultnum.
	 */
	addli   r0, r0, PTREGS_OFFSET_LR - (PTREGS_SIZE + KSTK_PTREGS_GAP)
	wh64    r0    /* cache line 3 */
	{
	 sw     r0, lr
	 addli  r0, r0, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
	}
	{
	 sw     r0, sp
	 addli  sp, r0, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_SP
	}
	{
	 sw     sp, r52
	 addli  sp, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(52)
	}
	wh64    sp    /* cache line 0 */
	{
	 sw     sp, r1
	 addli  sp, sp, PTREGS_OFFSET_REG(2) - PTREGS_OFFSET_REG(1)
	}
	{
	 sw     sp, r2
	 addli  sp, sp, PTREGS_OFFSET_REG(3) - PTREGS_OFFSET_REG(2)
	}
	{
	 sw     sp, r3
	 addli  sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3)
	}
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	mfspr   r0, SPR_EX_CONTEXT_K_0
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	.ifc \processing,handle_syscall
	/*
	 * Bump the saved PC by one bundle so that when we return, we won't
	 * execute the same swint instruction again.  We need to do this while
	 * we're in the critical section.
	 */
	addi    r0, r0, 8
	.endif
	{
	 sw     sp, r0
	 addli  sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
	}
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	mfspr   r0, SPR_EX_CONTEXT_K_1
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	{
	 sw     sp, r0
	 addi   sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
	/*
	 * Use r0 for syscalls so it's a temporary; use r1 for interrupts
	 * so that it gets passed through unchanged to the handler routine.
	 * Note that the .if conditional confusingly spans bundles.
	 */
	 .ifc \processing,handle_syscall
	 movei  r0, \vecnum
	}
	{
	 sw     sp, r0
	 .else
	 movei  r1, \vecnum
	}
	{
	 sw     sp, r1
	 .endif
	 addli  sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM
	}
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	mfspr   r0, SPR_SYSTEM_SAVE_K_1    /* Original r0 */
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	{
	 sw     sp, r0
	 addi   sp, sp, -PTREGS_OFFSET_REG(0) - 4
	}
	{
	 sw     sp, zero        /* write zero into "Next SP" frame pointer */
	 addi   sp, sp, -4      /* leave SP pointing at bottom of frame */
	}
	.ifc \processing,handle_syscall
	j       handle_syscall
	.else
	/*
	 * Capture per-interrupt SPR context to registers.
	 * We overload the meaning of r3 on this path such that if its bit 31
	 * is set, we have to mask all interrupts including NMIs before
	 * clearing the interrupt critical section bit.
	 * See discussion below at "finish_interrupt_save".
	 */
	.ifc \c_routine, do_page_fault
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	mfspr   r2, SPR_SYSTEM_SAVE_K_3   /* address of page fault */
	mfspr   r3, SPR_SYSTEM_SAVE_K_2   /* info about page fault */
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	.else
	.ifc \vecnum, INT_DOUBLE_FAULT
	{
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	 mfspr  r2, SPR_SYSTEM_SAVE_K_2   /* double fault info from HV */
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	 movei  r3, 0
	}
	.else
	.ifc \c_routine, do_trap
	{
	 mfspr  r2, GPV_REASON
	 movei  r3, 0
	}
	.else
	.ifc \c_routine, op_handle_perf_interrupt
	{
	 mfspr  r2, PERF_COUNT_STS
	 movei  r3, -1   /* not used, but set for consistency */
	}
	.else
#if CHIP_HAS_AUX_PERF_COUNTERS()
	.ifc \c_routine, op_handle_aux_perf_interrupt
	{
	 mfspr  r2, AUX_PERF_COUNT_STS
	 movei  r3, -1   /* not used, but set for consistency */
	}
	.else
#endif
	movei   r3, 0
#if CHIP_HAS_AUX_PERF_COUNTERS()
	.endif
#endif
	.endif
	.endif
	.endif
	.endif
	/* Put function pointer in r0 */
	moveli  r0, lo16(\c_routine)
	{
	 auli   r0, r0, ha16(\c_routine)
	 j       \processing
	}
	.endif
	ENDPROC(intvec_\vecname)

#ifdef __COLLECT_LINKER_FEEDBACK__
	.pushsection .text.intvec_feedback,"ax"
	.org    (\vecnum << 5)
	FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt1, 1 << 8)
	jrp     lr
	.popsection
#endif

	.endm


	/*
	 * Save the rest of the registers that we didn't save in the actual
	 * vector itself.  We can't use r0-r10 inclusive here.
	 */
	.macro  finish_interrupt_save, function

	/* If it's a syscall, save a proper orig_r0, otherwise just zero. */
	PTREGS_PTR(r52, PTREGS_OFFSET_ORIG_R0)
	{
	 .ifc \function,handle_syscall
	 sw     r52, r0
	 .else
	 sw     r52, zero
	 .endif
	 PTREGS_PTR(r52, PTREGS_OFFSET_TP)
	}

	/*
	 * For ordinary syscalls, we save neither caller- nor callee-
	 * save registers, since the syscall invoker doesn't expect the
	 * caller-saves to be saved, and the called kernel functions will
	 * take care of saving the callee-saves for us.
	 *
	 * For interrupts we save just the caller-save registers.  Saving
	 * them is required (since the "caller" can't save them).  Again,
	 * the called kernel functions will restore the callee-save
	 * registers for us appropriately.
	 *
	 * On return, we normally restore nothing special for syscalls,
	 * and just the caller-save registers for interrupts.
	 *
	 * However, there are some important caveats to all this:
	 *
	 * - We always save a few callee-save registers to give us
	 *   some scratchpad registers to carry across function calls.
	 *
	 * - fork/vfork/etc require us to save all the callee-save
	 *   registers, which we do in PTREGS_SYSCALL_ALL_REGS, below.
	 *
	 * - We always save r0..r5 and r10 for syscalls, since we need
	 *   to reload them a bit later for the actual kernel call, and
	 *   since we might need them for -ERESTARTNOINTR, etc.
	 *
	 * - Before invoking a signal handler, we save the unsaved
	 *   callee-save registers so they are visible to the
	 *   signal handler or any ptracer.
	 *
	 * - If the unsaved callee-save registers are modified, we set
	 *   a bit in pt_regs so we know to reload them from pt_regs
	 *   and not just rely on the kernel function unwinding.
	 *   (Done for ptrace register writes and SA_SIGINFO handler.)
	 */
	{
	 sw     r52, tp
	 PTREGS_PTR(r52, PTREGS_OFFSET_REG(33))
	}
	wh64    r52    /* cache line 2 */
	push_reg r33, r52
	push_reg r32, r52
	push_reg r31, r52
	.ifc \function,handle_syscall
	push_reg r30, r52, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(30)
	push_reg TREG_SYSCALL_NR_NAME, r52, \
	  PTREGS_OFFSET_REG(5) - PTREGS_OFFSET_SYSCALL
	.else

	push_reg r30, r52, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(30)
	wh64    r52    /* cache line 1 */
	push_reg r29, r52
	push_reg r28, r52
	push_reg r27, r52
	push_reg r26, r52
	push_reg r25, r52
	push_reg r24, r52
	push_reg r23, r52
	push_reg r22, r52
	push_reg r21, r52
	push_reg r20, r52
	push_reg r19, r52
	push_reg r18, r52
	push_reg r17, r52
	push_reg r16, r52
	push_reg r15, r52
	push_reg r14, r52
	push_reg r13, r52
	push_reg r12, r52
	push_reg r11, r52
	push_reg r10, r52
	push_reg r9, r52
	push_reg r8, r52
	push_reg r7, r52
	push_reg r6, r52

	.endif

	push_reg r5, r52
	sw      r52, r4

	/* Load tp with our per-cpu offset. */
#ifdef CONFIG_SMP
	{
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	 mfspr  r20, SPR_SYSTEM_SAVE_K_0
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	 moveli r21, lo16(__per_cpu_offset)
	}
	{
	 auli   r21, r21, ha16(__per_cpu_offset)
	 mm     r20, r20, zero, 0, LOG2_THREAD_SIZE-1
	}
	s2a     r20, r20, r21
	lw      tp, r20
#else
	move    tp, zero
#endif

	/*
	 * If we will be returning to the kernel, we will need to
	 * reset the interrupt masks to the state they had before.
	 * Set DISABLE_IRQ in flags iff we came from PL1 with irqs disabled.
	 * We load flags in r32 here so we can jump to .Lrestore_regs
	 * directly after do_page_fault_ics() if necessary.
	 */
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	mfspr   r32, SPR_EX_CONTEXT_K_1
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	{
	 andi   r32, r32, SPR_EX_CONTEXT_1_1__PL_MASK  /* mask off ICS */
	 PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS)
	}
	bzt     r32, 1f       /* zero if from user space */
	IRQS_DISABLED(r32)    /* zero if irqs enabled */
#if PT_FLAGS_DISABLE_IRQ != 1
# error Value of IRQS_DISABLED used to set PT_FLAGS_DISABLE_IRQ; fix
#endif
1:
	.ifnc \function,handle_syscall
	/* Record the fact that we saved the caller-save registers above. */
	ori     r32, r32, PT_FLAGS_CALLER_SAVES
	.endif
	sw      r21, r32

#ifdef __COLLECT_LINKER_FEEDBACK__
	/*
	 * Notify the feedback routines that we were in the
	 * appropriate fixed interrupt vector area.  Note that we
	 * still have ICS set at this point, so we can't invoke any
	 * atomic operations or we will panic.  The feedback
	 * routines internally preserve r0..r10 and r30 up.
	 */
	.ifnc \function,handle_syscall
	shli    r20, r1, 5
	.else
	moveli  r20, INT_SWINT_1 << 5
	.endif
	addli   r20, r20, lo16(intvec_feedback)
	auli    r20, r20, ha16(intvec_feedback)
	jalr    r20

	/* And now notify the feedback routines that we are here. */
	FEEDBACK_ENTER(\function)
#endif

	/*
	 * we've captured enough state to the stack (including in
	 * particular our EX_CONTEXT state) that we can now release
	 * the interrupt critical section and replace it with our
	 * standard "interrupts disabled" mask value.  This allows
	 * synchronous interrupts (and profile interrupts) to punch
	 * through from this point onwards.
	 *
	 * If bit 31 of r3 is set during a non-NMI interrupt, we know we
	 * are on the path where the hypervisor has punched through our
	 * ICS with a page fault, so we call out to do_page_fault_ics()
	 * to figure out what to do with it.  If the fault was in
	 * an atomic op, we unlock the atomic lock, adjust the
	 * saved register state a little, and return "zero" in r4,
	 * falling through into the normal page-fault interrupt code.
	 * If the fault was in a kernel-space atomic operation, then
	 * do_page_fault_ics() resolves it itself, returns "one" in r4,
	 * and as a result goes directly to restoring registers and iret,
	 * without trying to adjust the interrupt masks at all.
	 * The do_page_fault_ics() API involves passing and returning
	 * a five-word struct (in registers) to avoid writing the
	 * save and restore code here.
	 */
	.ifc \function,handle_nmi
	IRQ_DISABLE_ALL(r20)
	.else
	.ifnc \function,handle_syscall
	bgezt   r3, 1f
	{
	 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
	 jal    do_page_fault_ics
	}
	FEEDBACK_REENTER(\function)
	bzt     r4, 1f
	j       .Lrestore_regs
1:
	.endif
	IRQ_DISABLE(r20, r21)
	.endif
	mtspr   INTERRUPT_CRITICAL_SECTION, zero

#if CHIP_HAS_WH64()
	/*
	 * Prepare the first 256 stack bytes to be rapidly accessible
	 * without having to fetch the background data.  We don't really
	 * know how far to write-hint, but kernel stacks generally
	 * aren't that big, and write-hinting here does take some time.
	 */
	addi    r52, sp, -64
	{
	 wh64   r52
	 addi   r52, r52, -64
	}
	{
	 wh64   r52
	 addi   r52, r52, -64
	}
	{
	 wh64   r52
	 addi   r52, r52, -64
	}
	wh64    r52
#endif

#ifdef CONFIG_TRACE_IRQFLAGS
	.ifnc \function,handle_nmi
	/*
	 * We finally have enough state set up to notify the irq
	 * tracing code that irqs were disabled on entry to the handler.
	 * The TRACE_IRQS_OFF call clobbers registers r0-r29.
	 * For syscalls, we already have the register state saved away
	 * on the stack, so we don't bother to do any register saves here,
	 * and later we pop the registers back off the kernel stack.
	 * For interrupt handlers, save r0-r3 in callee-saved registers.
	 */
	.ifnc \function,handle_syscall
	{ move r30, r0; move r31, r1 }
	{ move r32, r2; move r33, r3 }
	.endif
	TRACE_IRQS_OFF
	.ifnc \function,handle_syscall
	{ move r0, r30; move r1, r31 }
	{ move r2, r32; move r3, r33 }
	.endif
	.endif
#endif

	.endm

	.macro  check_single_stepping, kind, not_single_stepping
	/*
	 * Check for single stepping in user-level priv
	 *   kind can be "normal", "ill", or "syscall"
	 * At end, if fall-thru
	 *   r29: thread_info->step_state
	 *   r28: &pt_regs->pc
	 *   r27: pt_regs->pc
	 *   r26: thread_info->step_state->buffer
	 */

	/* Check for single stepping */
	GET_THREAD_INFO(r29)
	{
	 /* Get pointer to field holding step state */
	 addi   r29, r29, THREAD_INFO_STEP_STATE_OFFSET

	 /* Get pointer to EX1 in register state */
	 PTREGS_PTR(r27, PTREGS_OFFSET_EX1)
	}
	{
	 /* Get pointer to field holding PC */
	 PTREGS_PTR(r28, PTREGS_OFFSET_PC)

	 /* Load the pointer to the step state */
	 lw     r29, r29
	}
	/* Load EX1 */
	lw      r27, r27
	{
	 /* Points to flags */
	 addi   r23, r29, SINGLESTEP_STATE_FLAGS_OFFSET

	 /* No single stepping if there is no step state structure */
	 bzt    r29, \not_single_stepping
	}
	{
	 /* mask off ICS and any other high bits */
	 andi   r27, r27, SPR_EX_CONTEXT_1_1__PL_MASK

	 /* Load pointer to single step instruction buffer */
	 lw     r26, r29
	}
	/* Check priv state */
	bnz     r27, \not_single_stepping

	/* Get flags */
	lw      r22, r23
	{
	 /* Branch if single-step mode not enabled */
	 bbnst  r22, \not_single_stepping

	 /* Clear enabled flag */
	 andi   r22, r22, ~SINGLESTEP_STATE_MASK_IS_ENABLED
	}
	.ifc \kind,normal
	{
	 /* Load PC */
	 lw     r27, r28

	 /* Point to the entry containing the original PC */
	 addi   r24, r29, SINGLESTEP_STATE_ORIG_PC_OFFSET
	}
	{
	 /* Disable single stepping flag */
	 sw     r23, r22
	}
	{
	 /* Get the original pc */
	 lw     r24, r24

	 /* See if the PC is at the start of the single step buffer */
	 seq    r25, r26, r27
	}
	/*
	 * NOTE: it is really expected that the PC be in the single step buffer
	 *       at this point
	 */
	bzt     r25, \not_single_stepping

	/* Restore the original PC */
	sw      r28, r24
	.else
	.ifc \kind,syscall
	{
	 /* Load PC */
	 lw     r27, r28

	 /* Point to the entry containing the next PC */
	 addi   r24, r29, SINGLESTEP_STATE_NEXT_PC_OFFSET
	}
	{
	 /* Increment the stopped PC by the bundle size */
	 addi   r26, r26, 8

	 /* Disable single stepping flag */
	 sw     r23, r22
	}
	{
	 /* Get the next pc */
	 lw     r24, r24

	 /*
	  * See if the PC is one bundle past the start of the
	  * single step buffer
	  */
	 seq    r25, r26, r27
	}
	{
	 /*
	  * NOTE: it is really expected that the PC be in the
	  * single step buffer at this point
	  */
	 bzt    r25, \not_single_stepping
	}
	/* Set to the next PC */
	sw      r28, r24
	.else
	{
	 /* Point to 3rd bundle in buffer */
	 addi   r25, r26, 16

	 /* Load PC */
	 lw      r27, r28
	}
	{
	 /* Disable single stepping flag */
	 sw      r23, r22

	 /* See if the PC is in the single step buffer */
	 slte_u  r24, r26, r27
	}
	{
	 slte_u r25, r27, r25

	 /*
	  * NOTE: it is really expected that the PC be in the
	  * single step buffer at this point
	  */
	 bzt    r24, \not_single_stepping
	}
	bzt     r25, \not_single_stepping
	.endif
	.endif
	.endm

	/*
	 * Redispatch a downcall.
	 */
	.macro  dc_dispatch vecnum, vecname
	.org    (\vecnum << 8)
intvec_\vecname:
	j       hv_downcall_dispatch
	ENDPROC(intvec_\vecname)
	.endm

	/*
	 * Common code for most interrupts.  The C function we're eventually
	 * going to is in r0, and the faultnum is in r1; the original
	 * values for those registers are on the stack.
	 */
	.pushsection .text.handle_interrupt,"ax"
handle_interrupt:
	finish_interrupt_save handle_interrupt

	/*
	 * Check for if we are single stepping in user level. If so, then
	 * we need to restore the PC.
	 */

	check_single_stepping normal, .Ldispatch_interrupt
.Ldispatch_interrupt:

	/* Jump to the C routine; it should enable irqs as soon as possible. */
	{
	 jalr   r0
	 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
	}
	FEEDBACK_REENTER(handle_interrupt)
	{
	 movei  r30, 0   /* not an NMI */
	 j      interrupt_return
	}
	STD_ENDPROC(handle_interrupt)

/*
 * This routine takes a boolean in r30 indicating if this is an NMI.
 * If so, we also expect a boolean in r31 indicating whether to
 * re-enable the oprofile interrupts.
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 *
 * Note that .Lresume_userspace is jumped to directly in several
 * places, and we need to make sure r30 is set correctly in those
 * callers as well.
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 */
STD_ENTRY(interrupt_return)
	/* If we're resuming to kernel space, don't check thread flags. */
	{
	 bnz    r30, .Lrestore_all  /* NMIs don't special-case user-space */
	 PTREGS_PTR(r29, PTREGS_OFFSET_EX1)
	}
	lw      r29, r29
	andi    r29, r29, SPR_EX_CONTEXT_1_1__PL_MASK  /* mask off ICS */
	{
	 bzt    r29, .Lresume_userspace
	 PTREGS_PTR(r29, PTREGS_OFFSET_PC)
	}

	/* If we're resuming to _cpu_idle_nap, bump PC forward by 8. */
	{
	 lw     r28, r29
	 moveli r27, lo16(_cpu_idle_nap)
	}
	{
	 auli   r27, r27, ha16(_cpu_idle_nap)
	}
	{
	 seq    r27, r27, r28
	}
	{
	 bbns   r27, .Lrestore_all
	 addi   r28, r28, 8
	}
	sw      r29, r28
	j       .Lrestore_all

.Lresume_userspace:
	FEEDBACK_REENTER(interrupt_return)

	/*
	 * Disable interrupts so as to make sure we don't
	 * miss an interrupt that sets any of the thread flags (like
	 * need_resched or sigpending) between sampling and the iret.
	 * Routines like schedule() or do_signal() may re-enable
	 * interrupts before returning.
	 */
	IRQ_DISABLE(r20, r21)
	TRACE_IRQS_OFF  /* Note: clobbers registers r0-r29 */

	/* Get base of stack in r32; note r30/31 are used as arguments here. */
	GET_THREAD_INFO(r32)


	/* Check to see if there is any work to do before returning to user. */
	{
	 addi   r29, r32, THREAD_INFO_FLAGS_OFFSET
858
	 moveli r1, lo16(_TIF_ALLWORK_MASK)
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861
	}
	{
	 lw     r29, r29
862
	 auli   r1, r1, ha16(_TIF_ALLWORK_MASK)
863
	}
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	and     r1, r29, r1
	bzt     r1, .Lrestore_all

	/*
	 * Make sure we have all the registers saved for signal
	 * handling or single-step.  Call out to C code to figure out
	 * exactly what we need to do for each flag bit, then if
	 * necessary, reload the flags and recheck.
	 */
	push_extra_callee_saves r0
	{
	 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
	 jal    do_work_pending
	}
	bnz     r0, .Lresume_userspace
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	/*
	 * In the NMI case we
	 * omit the call to single_process_check_nohz, which normally checks
	 * to see if we should start or stop the scheduler tick, because
	 * we can't call arbitrary Linux code from an NMI context.
	 * We always call the homecache TLB deferral code to re-trigger
	 * the deferral mechanism.
	 *
	 * The other chunk of responsibility this code has is to reset the
	 * interrupt masks appropriately to reset irqs and NMIs.  We have
	 * to call TRACE_IRQS_OFF and TRACE_IRQS_ON to support all the
	 * lockdep-type stuff, but we can't set ICS until afterwards, since
	 * ICS can only be used in very tight chunks of code to avoid
	 * tripping over various assertions that it is off.
	 *
	 * (There is what looks like a window of vulnerability here since
	 * we might take a profile interrupt between the two SPR writes
	 * that set the mask, but since we write the low SPR word first,
	 * and our interrupt entry code checks the low SPR word, any
	 * profile interrupt will actually disable interrupts in both SPRs
	 * before returning, which is OK.)
	 */
.Lrestore_all:
	PTREGS_PTR(r0, PTREGS_OFFSET_EX1)
	{
	 lw     r0, r0
	 PTREGS_PTR(r32, PTREGS_OFFSET_FLAGS)
	}
	{
	 andi   r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK
	 lw     r32, r32
	}
	bnz    r0, 1f
	j       2f
#if PT_FLAGS_DISABLE_IRQ != 1
# error Assuming PT_FLAGS_DISABLE_IRQ == 1 so we can use bbnst below
#endif
1:	bbnst   r32, 2f
	IRQ_DISABLE(r20,r21)
	TRACE_IRQS_OFF
	movei   r0, 1
	mtspr   INTERRUPT_CRITICAL_SECTION, r0
	bzt     r30, .Lrestore_regs
	j       3f
2:	TRACE_IRQS_ON
	movei   r0, 1
	mtspr   INTERRUPT_CRITICAL_SECTION, r0
	IRQ_ENABLE(r20, r21)
	bzt     r30, .Lrestore_regs
3:


	/*
	 * We now commit to returning from this interrupt, since we will be
	 * doing things like setting EX_CONTEXT SPRs and unwinding the stack
	 * frame.  No calls should be made to any other code after this point.
	 * This code should only be entered with ICS set.
	 * r32 must still be set to ptregs.flags.
	 * We launch loads to each cache line separately first, so we can
	 * get some parallelism out of the memory subsystem.
	 * We start zeroing caller-saved registers throughout, since
	 * that will save some cycles if this turns out to be a syscall.
	 */
.Lrestore_regs:
	FEEDBACK_REENTER(interrupt_return)   /* called from elsewhere */

	/*
	 * Rotate so we have one high bit and one low bit to test.
	 * - low bit says whether to restore all the callee-saved registers,
	 *   or just r30-r33, and r52 up.
	 * - high bit (i.e. sign bit) says whether to restore all the
	 *   caller-saved registers, or just r0.
	 */
#if PT_FLAGS_CALLER_SAVES != 2 || PT_FLAGS_RESTORE_REGS != 4
# error Rotate trick does not work :-)
#endif
	{
	 rli    r20, r32, 30
	 PTREGS_PTR(sp, PTREGS_OFFSET_REG(0))
	}

	/*
	 * Load cache lines 0, 2, and 3 in that order, then use
	 * the last loaded value, which makes it likely that the other
	 * cache lines have also loaded, at which point we should be
	 * able to safely read all the remaining words on those cache
	 * lines without waiting for the memory subsystem.
	 */
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	pop_reg_zero r0, r28, sp, PTREGS_OFFSET_REG(30) - PTREGS_OFFSET_REG(0)
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	pop_reg_zero r30, r2, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(30)
	pop_reg_zero r21, r3, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
	pop_reg_zero lr, r4, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_EX1
	{
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	 mtspr  SPR_EX_CONTEXT_K_0, r21
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	 move   r5, zero
	}
	{
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	 mtspr  SPR_EX_CONTEXT_K_1, lr
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	 andi   lr, lr, SPR_EX_CONTEXT_1_1__PL_MASK  /* mask off ICS */
	}

	/* Restore callee-saveds that we actually use. */
	pop_reg_zero r52, r6, sp, PTREGS_OFFSET_REG(31) - PTREGS_OFFSET_REG(52)
	pop_reg_zero r31, r7
	pop_reg_zero r32, r8
	pop_reg_zero r33, r9, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(33)

	/*
	 * If we modified other callee-saveds, restore them now.
	 * This is rare, but could be via ptrace or signal handler.
	 */
	{
	 move   r10, zero
	 bbs    r20, .Lrestore_callees
	}
.Lcontinue_restore_regs:

	/* Check if we're returning from a syscall. */
	{
	 move   r11, zero
	 blzt   r20, 1f  /* no, so go restore callee-save registers */