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st,clkgen.txt 1.94 KB
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Binding for a Clockgen hardware block found on
certain STMicroelectronics consumer electronics SoC devices.

A Clockgen node can contain pll, diviser or multiplexer nodes.

We will find only the base address of the Clockgen, this base
address is common of all subnode.

	clockgen_node {
		reg = <>;

		pll_node {
			...
		};

		prediv_node {
			...
		};

		divmux_node {
			...
		};

		quadfs_node {
			...
		};
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		mux_node {
			...
		};

		vcc_node {
			...
		};
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		...
	};

This binding uses the common clock binding[1].
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Each subnode should use the binding discribe in [2]..[7]
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
[6] Documentation/devicetree/bindings/clock/st,vcc.txt
[7] Documentation/devicetree/bindings/clock/st,quadfs.txt

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Required properties:
- reg : A Base address and length of the register set.

Example:

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	clockgen-a@fee62000 {
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		reg = <0xfee62000 0xb48>;

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		clk_s_a0_pll: clk-s-a0-pll {
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			#clock-cells = <1>;
			compatible = "st,clkgena-plls-c65";

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			clocks = <&clk-sysin>;
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			clock-output-names = "clk-s-a0-pll0-hs",
					     "clk-s-a0-pll0-ls",
					     "clk-s-a0-pll1";
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		};

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		clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
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			#clock-cells = <0>;
			compatible = "st,clkgena-prediv-c65",
				     "st,clkgena-prediv";

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			clocks = <&clk_sysin>;
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			clock-output-names = "clk-s-a0-osc-prediv";
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		};

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		clk_s_a0_hs: clk-s-a0-hs {
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			#clock-cells = <1>;
			compatible = "st,clkgena-divmux-c65-hs",
				     "st,clkgena-divmux";

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			clocks = <&clk-s_a0_osc_prediv>,
				 <&clk-s_a0_pll 0>, /* pll0 hs */
				 <&clk-s_a0_pll 2>; /* pll1 */
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			clock-output-names = "clk-s-fdma-0",
					     "clk-s-fdma-1",
					     ""; /* clk-s-jit-sense */
					     /* fourth output unused */
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		};
	};