eswitch_offloads.c 69 KB
Newer Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
/*
 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/etherdevice.h>
#include <linux/mlx5/driver.h>
#include <linux/mlx5/mlx5_ifc.h>
#include <linux/mlx5/vport.h>
#include <linux/mlx5/fs.h>
#include "mlx5_core.h"
#include "eswitch.h"
40
#include "rdma.h"
41
42
#include "en.h"
#include "fs_core.h"
43
#include "lib/devcom.h"
44
#include "lib/eq.h"
45

46
47
48
49
50
/* There are two match-all miss flows, one for unicast dst mac and
 * one for multicast.
 */
#define MLX5_ESW_MISS_FLOWS (2)

51
52
53
#define fdb_prio_table(esw, chain, prio, level) \
	(esw)->fdb_table.offloads.fdb_prio[(chain)][(prio)][(level)]

54
55
#define UPLINK_REP_INDEX 0

56
57
58
static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
						     u16 vport_num)
{
59
	u16 idx = mlx5_eswitch_vport_num_to_index(esw, vport_num);
60
61
62
63
64

	WARN_ON(idx > esw->total_vports - 1);
	return &esw->offloads.vport_reps[idx];
}

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
static struct mlx5_flow_table *
esw_get_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level);
static void
esw_put_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level);

bool mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw)
{
	return (!!(esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED));
}

u32 mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw)
{
	if (esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED)
		return FDB_MAX_CHAIN;

	return 0;
}

u16 mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw)
{
	if (esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED)
		return FDB_MAX_PRIO;

88
	return 1;
89
90
}

91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
static void
mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
				  struct mlx5_flow_spec *spec,
				  struct mlx5_esw_flow_attr *attr)
{
	void *misc2;
	void *misc;

	/* Use metadata matching because vport is not represented by single
	 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
	 */
	if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
		misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
		MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
			 mlx5_eswitch_get_vport_metadata_for_match(attr->in_mdev->priv.eswitch,
								   attr->in_rep->vport));

		misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
		MLX5_SET_TO_ONES(fte_match_set_misc2, misc2, metadata_reg_c_0);

		spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
		misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
		if (memchr_inv(misc, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc)))
			spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
	} else {
		misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
		MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport);

		if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
			MLX5_SET(fte_match_set_misc, misc,
				 source_eswitch_owner_vhca_id,
				 MLX5_CAP_GEN(attr->in_mdev, vhca_id));

		misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
		MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
		if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
			MLX5_SET_TO_ONES(fte_match_set_misc, misc,
					 source_eswitch_owner_vhca_id);

		spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
	}

	if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
	    attr->in_rep->vport == MLX5_VPORT_UPLINK)
		spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK;
}

Mark Bloch's avatar
Mark Bloch committed
138
struct mlx5_flow_handle *
139
140
mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
				struct mlx5_flow_spec *spec,
141
				struct mlx5_esw_flow_attr *attr)
142
{
143
	struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
144
	struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
145
	bool split = !!(attr->split_count);
Mark Bloch's avatar
Mark Bloch committed
146
	struct mlx5_flow_handle *rule;
147
	struct mlx5_flow_table *fdb;
148
	int j, i = 0;
149
150
151
152

	if (esw->mode != SRIOV_OFFLOADS)
		return ERR_PTR(-EOPNOTSUPP);

153
154
	flow_act.action = attr->action;
	/* if per flow vlan pop/push is emulated, don't set that into the firmware */
155
	if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
156
157
158
		flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
				     MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
	else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
159
160
161
		flow_act.vlan[0].ethtype = ntohs(attr->vlan_proto[0]);
		flow_act.vlan[0].vid = attr->vlan_vid[0];
		flow_act.vlan[0].prio = attr->vlan_prio[0];
162
163
164
165
166
		if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
			flow_act.vlan[1].ethtype = ntohs(attr->vlan_proto[1]);
			flow_act.vlan[1].vid = attr->vlan_vid[1];
			flow_act.vlan[1].prio = attr->vlan_prio[1];
		}
167
	}
168

169
	if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
170
171
172
173
174
175
176
177
178
179
180
		if (attr->dest_chain) {
			struct mlx5_flow_table *ft;

			ft = esw_get_prio_table(esw, attr->dest_chain, 1, 0);
			if (IS_ERR(ft)) {
				rule = ERR_CAST(ft);
				goto err_create_goto_table;
			}

			dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
			dest[i].ft = ft;
181
			i++;
182
		} else {
183
			for (j = attr->split_count; j < attr->out_count; j++) {
184
				dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
185
				dest[i].vport.num = attr->dests[j].rep->vport;
186
				dest[i].vport.vhca_id =
187
					MLX5_CAP_GEN(attr->dests[j].mdev, vhca_id);
188
189
190
				if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
					dest[i].vport.flags |=
						MLX5_FLOW_DEST_VPORT_VHCA_ID;
191
192
				if (attr->dests[j].flags & MLX5_ESW_DEST_ENCAP) {
					flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
193
					flow_act.reformat_id = attr->dests[j].encap_id;
194
					dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
195
196
					dest[i].vport.reformat_id =
						attr->dests[j].encap_id;
197
				}
198
199
				i++;
			}
200
		}
201
	}
202
	if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
203
		dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
204
		dest[i].counter_id = mlx5_fc_id(attr->counter);
205
		i++;
206
207
	}

208
	mlx5_eswitch_set_rule_source_port(esw, spec, attr);
209

210
211
212
213
214
215
216
217
	if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DECAP) {
		if (attr->tunnel_match_level != MLX5_MATCH_NONE)
			spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
		if (attr->match_level != MLX5_MATCH_NONE)
			spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
	} else if (attr->match_level != MLX5_MATCH_NONE) {
		spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
	}
218

219
	if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
220
221
		flow_act.modify_id = attr->mod_hdr_id;

222
	fdb = esw_get_prio_table(esw, attr->chain, attr->prio, !!split);
223
224
225
226
227
228
	if (IS_ERR(fdb)) {
		rule = ERR_CAST(fdb);
		goto err_esw_get;
	}

	rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
229
	if (IS_ERR(rule))
230
		goto err_add_rule;
231
232
	else
		esw->offloads.num_flows++;
233

234
235
236
	return rule;

err_add_rule:
237
	esw_put_prio_table(esw, attr->chain, attr->prio, !!split);
238
239
240
241
err_esw_get:
	if (attr->dest_chain)
		esw_put_prio_table(esw, attr->dest_chain, 1, 0);
err_create_goto_table:
242
	return rule;
243
244
}

245
246
247
248
249
250
struct mlx5_flow_handle *
mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
			  struct mlx5_flow_spec *spec,
			  struct mlx5_esw_flow_attr *attr)
{
	struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
251
	struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
252
253
	struct mlx5_flow_table *fast_fdb;
	struct mlx5_flow_table *fwd_fdb;
254
255
256
	struct mlx5_flow_handle *rule;
	int i;

257
258
259
260
261
262
263
264
265
266
267
268
	fast_fdb = esw_get_prio_table(esw, attr->chain, attr->prio, 0);
	if (IS_ERR(fast_fdb)) {
		rule = ERR_CAST(fast_fdb);
		goto err_get_fast;
	}

	fwd_fdb = esw_get_prio_table(esw, attr->chain, attr->prio, 1);
	if (IS_ERR(fwd_fdb)) {
		rule = ERR_CAST(fwd_fdb);
		goto err_get_fwd;
	}

269
	flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
270
	for (i = 0; i < attr->split_count; i++) {
271
		dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
272
		dest[i].vport.num = attr->dests[i].rep->vport;
273
		dest[i].vport.vhca_id =
274
			MLX5_CAP_GEN(attr->dests[i].mdev, vhca_id);
275
276
		if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
			dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
277
278
		if (attr->dests[i].flags & MLX5_ESW_DEST_ENCAP) {
			dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
279
			dest[i].vport.reformat_id = attr->dests[i].encap_id;
280
		}
281
282
	}
	dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
283
	dest[i].ft = fwd_fdb,
284
285
	i++;

286
	mlx5_eswitch_set_rule_source_port(esw, spec, attr);
287

288
289
	if (attr->match_level != MLX5_MATCH_NONE)
		spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
290

291
	rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
292

293
294
	if (IS_ERR(rule))
		goto add_err;
295

296
297
298
299
300
301
302
303
	esw->offloads.num_flows++;

	return rule;
add_err:
	esw_put_prio_table(esw, attr->chain, attr->prio, 1);
err_get_fwd:
	esw_put_prio_table(esw, attr->chain, attr->prio, 0);
err_get_fast:
304
305
306
	return rule;
}

307
308
309
310
311
312
static void
__mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
			struct mlx5_flow_handle *rule,
			struct mlx5_esw_flow_attr *attr,
			bool fwd_rule)
{
313
	bool split = (attr->split_count > 0);
314
315
316
317
318
319
320
321

	mlx5_del_flow_rules(rule);
	esw->offloads.num_flows--;

	if (fwd_rule)  {
		esw_put_prio_table(esw, attr->chain, attr->prio, 1);
		esw_put_prio_table(esw, attr->chain, attr->prio, 0);
	} else {
322
		esw_put_prio_table(esw, attr->chain, attr->prio, !!split);
323
324
325
326
327
		if (attr->dest_chain)
			esw_put_prio_table(esw, attr->dest_chain, 1, 0);
	}
}

328
329
330
331
332
void
mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
				struct mlx5_flow_handle *rule,
				struct mlx5_esw_flow_attr *attr)
{
333
	__mlx5_eswitch_del_rule(esw, rule, attr, false);
334
335
}

336
337
338
339
340
void
mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
			  struct mlx5_flow_handle *rule,
			  struct mlx5_esw_flow_attr *attr)
{
341
	__mlx5_eswitch_del_rule(esw, rule, attr, true);
342
343
}

344
345
346
347
348
349
350
351
static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
{
	struct mlx5_eswitch_rep *rep;
	int vf_vport, err = 0;

	esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
	for (vf_vport = 1; vf_vport < esw->enabled_vports; vf_vport++) {
		rep = &esw->offloads.vport_reps[vf_vport];
352
		if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
			continue;

		err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
		if (err)
			goto out;
	}

out:
	return err;
}

static struct mlx5_eswitch_rep *
esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
{
	struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;

	in_rep  = attr->in_rep;
370
	out_rep = attr->dests[0].rep;
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390

	if (push)
		vport = in_rep;
	else if (pop)
		vport = out_rep;
	else
		vport = in_rep;

	return vport;
}

static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
				     bool push, bool pop, bool fwd)
{
	struct mlx5_eswitch_rep *in_rep, *out_rep;

	if ((push || pop) && !fwd)
		goto out_notsupp;

	in_rep  = attr->in_rep;
391
	out_rep = attr->dests[0].rep;
392

393
	if (push && in_rep->vport == MLX5_VPORT_UPLINK)
394
395
		goto out_notsupp;

396
	if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
397
398
399
400
		goto out_notsupp;

	/* vport has vlan push configured, can't offload VF --> wire rules w.o it */
	if (!push && !pop && fwd)
401
		if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
402
403
404
405
406
			goto out_notsupp;

	/* protects against (1) setting rules with different vlans to push and
	 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
	 */
407
	if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
408
409
410
411
412
		goto out_notsupp;

	return 0;

out_notsupp:
413
	return -EOPNOTSUPP;
414
415
416
417
418
419
420
421
422
423
}

int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
				 struct mlx5_esw_flow_attr *attr)
{
	struct offloads_fdb *offloads = &esw->fdb_table.offloads;
	struct mlx5_eswitch_rep *vport = NULL;
	bool push, pop, fwd;
	int err = 0;

424
	/* nop if we're on the vlan push/pop non emulation mode */
425
	if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
426
427
		return 0;

428
429
	push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
	pop  = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
430
431
	fwd  = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
		   !attr->dest_chain);
432
433
434
435
436
437
438
439
440
441
442

	err = esw_add_vlan_action_check(attr, push, pop, fwd);
	if (err)
		return err;

	attr->vlan_handled = false;

	vport = esw_vlan_action_get_vport(attr, push, pop);

	if (!push && !pop && fwd) {
		/* tracks VF --> wire rules without vlan push action */
443
		if (attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
			vport->vlan_refcount++;
			attr->vlan_handled = true;
		}

		return 0;
	}

	if (!push && !pop)
		return 0;

	if (!(offloads->vlan_push_pop_refcount)) {
		/* it's the 1st vlan rule, apply global vlan pop policy */
		err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
		if (err)
			goto out;
	}
	offloads->vlan_push_pop_refcount++;

	if (push) {
		if (vport->vlan_refcount)
			goto skip_set_push;

466
		err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, attr->vlan_vid[0], 0,
467
468
469
						    SET_VLAN_INSERT | SET_VLAN_STRIP);
		if (err)
			goto out;
470
		vport->vlan = attr->vlan_vid[0];
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
skip_set_push:
		vport->vlan_refcount++;
	}
out:
	if (!err)
		attr->vlan_handled = true;
	return err;
}

int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
				 struct mlx5_esw_flow_attr *attr)
{
	struct offloads_fdb *offloads = &esw->fdb_table.offloads;
	struct mlx5_eswitch_rep *vport = NULL;
	bool push, pop, fwd;
	int err = 0;

488
	/* nop if we're on the vlan push/pop non emulation mode */
489
	if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
490
491
		return 0;

492
493
494
495
496
497
498
499
500
501
502
	if (!attr->vlan_handled)
		return 0;

	push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
	pop  = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
	fwd  = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);

	vport = esw_vlan_action_get_vport(attr, push, pop);

	if (!push && !pop && fwd) {
		/* tracks VF --> wire rules without vlan push action */
503
		if (attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
			vport->vlan_refcount--;

		return 0;
	}

	if (push) {
		vport->vlan_refcount--;
		if (vport->vlan_refcount)
			goto skip_unset_push;

		vport->vlan = 0;
		err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
						    0, 0, SET_VLAN_STRIP);
		if (err)
			goto out;
	}

skip_unset_push:
	offloads->vlan_push_pop_refcount--;
	if (offloads->vlan_push_pop_refcount)
		return 0;

	/* no more vlan rules, stop global vlan pop policy */
	err = esw_set_global_vlan_pop(esw, 0);

out:
	return err;
}

533
struct mlx5_flow_handle *
534
535
mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, int vport, u32 sqn)
{
536
	struct mlx5_flow_act flow_act = {0};
537
	struct mlx5_flow_destination dest = {};
Mark Bloch's avatar
Mark Bloch committed
538
	struct mlx5_flow_handle *flow_rule;
539
	struct mlx5_flow_spec *spec;
540
541
	void *misc;

542
	spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
543
	if (!spec) {
544
545
546
547
		flow_rule = ERR_PTR(-ENOMEM);
		goto out;
	}

548
	misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
549
	MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
550
551
	/* source vport is the esw manager */
	MLX5_SET(fte_match_set_misc, misc, source_port, esw->manager_vport);
552

553
	misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
554
555
556
	MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
	MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);

557
	spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
558
	dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
559
	dest.vport.num = vport;
560
	flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
561

562
	flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
563
					&flow_act, &dest, 1);
564
565
566
	if (IS_ERR(flow_rule))
		esw_warn(esw->dev, "FDB: Failed to add send to vport rule err %ld\n", PTR_ERR(flow_rule));
out:
567
	kvfree(spec);
568
569
	return flow_rule;
}
570
EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
571

572
573
574
575
576
void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
{
	mlx5_del_flow_rules(rule);
}

577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
static int mlx5_eswitch_enable_passing_vport_metadata(struct mlx5_eswitch *esw)
{
	u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
	u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
	u8 fdb_to_vport_reg_c_id;
	int err;

	err = mlx5_eswitch_query_esw_vport_context(esw, esw->manager_vport,
						   out, sizeof(out));
	if (err)
		return err;

	fdb_to_vport_reg_c_id = MLX5_GET(query_esw_vport_context_out, out,
					 esw_vport_context.fdb_to_vport_reg_c_id);

	fdb_to_vport_reg_c_id |= MLX5_FDB_TO_VPORT_REG_C_0;
	MLX5_SET(modify_esw_vport_context_in, in,
		 esw_vport_context.fdb_to_vport_reg_c_id, fdb_to_vport_reg_c_id);

	MLX5_SET(modify_esw_vport_context_in, in,
		 field_select.fdb_to_vport_reg_c_id, 1);

	return mlx5_eswitch_modify_esw_vport_context(esw, esw->manager_vport,
						     in, sizeof(in));
}

static int mlx5_eswitch_disable_passing_vport_metadata(struct mlx5_eswitch *esw)
{
	u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
	u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
	u8 fdb_to_vport_reg_c_id;
	int err;

	err = mlx5_eswitch_query_esw_vport_context(esw, esw->manager_vport,
						   out, sizeof(out));
	if (err)
		return err;

	fdb_to_vport_reg_c_id = MLX5_GET(query_esw_vport_context_out, out,
					 esw_vport_context.fdb_to_vport_reg_c_id);

	fdb_to_vport_reg_c_id &= ~MLX5_FDB_TO_VPORT_REG_C_0;

	MLX5_SET(modify_esw_vport_context_in, in,
		 esw_vport_context.fdb_to_vport_reg_c_id, fdb_to_vport_reg_c_id);

	MLX5_SET(modify_esw_vport_context_in, in,
		 field_select.fdb_to_vport_reg_c_id, 1);

	return mlx5_eswitch_modify_esw_vport_context(esw, esw->manager_vport,
						     in, sizeof(in));
}

630
631
static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
				  struct mlx5_core_dev *peer_dev,
632
633
634
				  struct mlx5_flow_spec *spec,
				  struct mlx5_flow_destination *dest)
{
635
	void *misc;
636

637
638
639
640
	if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
		misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
				    misc_parameters_2);
		MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
641

642
643
644
645
		spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
	} else {
		misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
				    misc_parameters);
646

647
648
649
650
651
652
653
654
655
656
657
		MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
			 MLX5_CAP_GEN(peer_dev, vhca_id));

		spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;

		misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
				    misc_parameters);
		MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
		MLX5_SET_TO_ONES(fte_match_set_misc, misc,
				 source_eswitch_owner_vhca_id);
	}
658
659

	dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
660
	dest->vport.num = peer_dev->priv.eswitch->manager_vport;
661
	dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
662
	dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
663
664
}

665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
					       struct mlx5_eswitch *peer_esw,
					       struct mlx5_flow_spec *spec,
					       u16 vport)
{
	void *misc;

	if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
		misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
				    misc_parameters_2);
		MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
			 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
								   vport));
	} else {
		misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
				    misc_parameters);
		MLX5_SET(fte_match_set_misc, misc, source_port, vport);
	}
}

685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
				       struct mlx5_core_dev *peer_dev)
{
	struct mlx5_flow_destination dest = {};
	struct mlx5_flow_act flow_act = {0};
	struct mlx5_flow_handle **flows;
	struct mlx5_flow_handle *flow;
	struct mlx5_flow_spec *spec;
	/* total vports is the same for both e-switches */
	int nvports = esw->total_vports;
	void *misc;
	int err, i;

	spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
	if (!spec)
		return -ENOMEM;

702
	peer_miss_rules_setup(esw, peer_dev, spec, &dest);
703
704
705
706
707
708
709
710
711
712
713

	flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
	if (!flows) {
		err = -ENOMEM;
		goto alloc_flows_err;
	}

	flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
	misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
			    misc_parameters);

714
	if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
715
716
717
		esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
						   spec, MLX5_VPORT_PF);

718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
		flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
					   spec, &flow_act, &dest, 1);
		if (IS_ERR(flow)) {
			err = PTR_ERR(flow);
			goto add_pf_flow_err;
		}
		flows[MLX5_VPORT_PF] = flow;
	}

	if (mlx5_ecpf_vport_exists(esw->dev)) {
		MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
		flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
					   spec, &flow_act, &dest, 1);
		if (IS_ERR(flow)) {
			err = PTR_ERR(flow);
			goto add_ecpf_flow_err;
		}
		flows[mlx5_eswitch_ecpf_idx(esw)] = flow;
	}

738
	mlx5_esw_for_each_vf_vport_num(esw, i, mlx5_core_max_vfs(esw->dev)) {
739
740
741
742
		esw_set_peer_miss_rule_source_port(esw,
						   peer_dev->priv.eswitch,
						   spec, i);

743
744
745
746
		flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
					   spec, &flow_act, &dest, 1);
		if (IS_ERR(flow)) {
			err = PTR_ERR(flow);
747
			goto add_vf_flow_err;
748
749
750
751
752
753
754
755
756
		}
		flows[i] = flow;
	}

	esw->fdb_table.offloads.peer_miss_rules = flows;

	kvfree(spec);
	return 0;

757
add_vf_flow_err:
758
	nvports = --i;
759
	mlx5_esw_for_each_vf_vport_num_reverse(esw, i, nvports)
760
		mlx5_del_flow_rules(flows[i]);
761
762
763
764
765
766
767
768

	if (mlx5_ecpf_vport_exists(esw->dev))
		mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
add_ecpf_flow_err:
	if (mlx5_core_is_ecpf_esw_manager(esw->dev))
		mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
add_pf_flow_err:
	esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
769
770
771
772
773
774
775
776
777
778
779
780
781
	kvfree(flows);
alloc_flows_err:
	kvfree(spec);
	return err;
}

static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
{
	struct mlx5_flow_handle **flows;
	int i;

	flows = esw->fdb_table.offloads.peer_miss_rules;

782
783
	mlx5_esw_for_each_vf_vport_num_reverse(esw, i,
					       mlx5_core_max_vfs(esw->dev))
784
785
		mlx5_del_flow_rules(flows[i]);

786
787
788
789
790
791
	if (mlx5_ecpf_vport_exists(esw->dev))
		mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);

	if (mlx5_core_is_ecpf_esw_manager(esw->dev))
		mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);

792
793
794
	kvfree(flows);
}

795
796
static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
{
797
	struct mlx5_flow_act flow_act = {0};
798
	struct mlx5_flow_destination dest = {};
Mark Bloch's avatar
Mark Bloch committed
799
	struct mlx5_flow_handle *flow_rule = NULL;
800
	struct mlx5_flow_spec *spec;
801
802
	void *headers_c;
	void *headers_v;
803
	int err = 0;
804
805
	u8 *dmac_c;
	u8 *dmac_v;
806

807
	spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
808
	if (!spec) {
809
810
811
812
		err = -ENOMEM;
		goto out;
	}

813
814
815
816
817
818
819
	spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
	headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
				 outer_headers);
	dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
			      outer_headers.dmac_47_16);
	dmac_c[0] = 0x01;

820
	dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
821
	dest.vport.num = esw->manager_vport;
822
	flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
823

824
	flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
825
					&flow_act, &dest, 1);
826
827
	if (IS_ERR(flow_rule)) {
		err = PTR_ERR(flow_rule);
828
		esw_warn(esw->dev,  "FDB: Failed to add unicast miss flow rule err %d\n", err);
829
830
831
		goto out;
	}

832
833
834
835
836
837
838
	esw->fdb_table.offloads.miss_rule_uni = flow_rule;

	headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
				 outer_headers);
	dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
			      outer_headers.dmac_47_16);
	dmac_v[0] = 0x01;
839
	flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
840
841
842
843
844
845
846
847
848
849
					&flow_act, &dest, 1);
	if (IS_ERR(flow_rule)) {
		err = PTR_ERR(flow_rule);
		esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
		mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
		goto out;
	}

	esw->fdb_table.offloads.miss_rule_multi = flow_rule;

850
out:
851
	kvfree(spec);
852
853
854
	return err;
}

855
#define ESW_OFFLOADS_NUM_GROUPS  4
856

857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
/* Firmware currently has 4 pool of 4 sizes that it supports (ESW_POOLS),
 * and a virtual memory region of 16M (ESW_SIZE), this region is duplicated
 * for each flow table pool. We can allocate up to 16M of each pool,
 * and we keep track of how much we used via put/get_sz_to_pool.
 * Firmware doesn't report any of this for now.
 * ESW_POOL is expected to be sorted from large to small
 */
#define ESW_SIZE (16 * 1024 * 1024)
const unsigned int ESW_POOLS[4] = { 4 * 1024 * 1024, 1 * 1024 * 1024,
				    64 * 1024, 4 * 1024 };

static int
get_sz_from_pool(struct mlx5_eswitch *esw)
{
	int sz = 0, i;

	for (i = 0; i < ARRAY_SIZE(ESW_POOLS); i++) {
		if (esw->fdb_table.offloads.fdb_left[i]) {
			--esw->fdb_table.offloads.fdb_left[i];
			sz = ESW_POOLS[i];
			break;
		}
	}

	return sz;
}

static void
put_sz_to_pool(struct mlx5_eswitch *esw, int sz)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(ESW_POOLS); i++) {
		if (sz >= ESW_POOLS[i]) {
			++esw->fdb_table.offloads.fdb_left[i];
			break;
		}
	}
}

static struct mlx5_flow_table *
create_next_size_table(struct mlx5_eswitch *esw,
		       struct mlx5_flow_namespace *ns,
		       u16 table_prio,
		       int level,
		       u32 flags)
{
	struct mlx5_flow_table *fdb;
	int sz;

	sz = get_sz_from_pool(esw);
	if (!sz)
		return ERR_PTR(-ENOSPC);

	fdb = mlx5_create_auto_grouped_flow_table(ns,
						  table_prio,
						  sz,
						  ESW_OFFLOADS_NUM_GROUPS,
						  level,
						  flags);
	if (IS_ERR(fdb)) {
		esw_warn(esw->dev, "Failed to create FDB Table err %d (table prio: %d, level: %d, size: %d)\n",
			 (int)PTR_ERR(fdb), table_prio, level, sz);
		put_sz_to_pool(esw, sz);
	}

	return fdb;
}

static struct mlx5_flow_table *
esw_get_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level)
928
929
930
{
	struct mlx5_core_dev *dev = esw->dev;
	struct mlx5_flow_table *fdb = NULL;
931
932
	struct mlx5_flow_namespace *ns;
	int table_prio, l = 0;
933
	u32 flags = 0;
934

935
936
937
	if (chain == FDB_SLOW_PATH_CHAIN)
		return esw->fdb_table.offloads.slow_fdb;

938
	mutex_lock(&esw->fdb_table.offloads.fdb_prio_lock);
939

940
941
942
943
944
945
946
947
	fdb = fdb_prio_table(esw, chain, prio, level).fdb;
	if (fdb) {
		/* take ref on earlier levels as well */
		while (level >= 0)
			fdb_prio_table(esw, chain, prio, level--).num_rules++;
		mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
		return fdb;
	}
948

949
950
951
952
953
954
	ns = mlx5_get_fdb_sub_ns(dev, chain);
	if (!ns) {
		esw_warn(dev, "Failed to get FDB sub namespace\n");
		mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
		return ERR_PTR(-EOPNOTSUPP);
	}
955

956
	if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
957
		flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
958
			  MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
959

960
	table_prio = (chain * FDB_MAX_PRIO) + prio - 1;
961

962
963
964
965
966
967
968
969
	/* create earlier levels for correct fs_core lookup when
	 * connecting tables
	 */
	for (l = 0; l <= level; l++) {
		if (fdb_prio_table(esw, chain, prio, l).fdb) {
			fdb_prio_table(esw, chain, prio, l).num_rules++;
			continue;
		}
970

971
972
973
974
975
976
977
978
		fdb = create_next_size_table(esw, ns, table_prio, l, flags);
		if (IS_ERR(fdb)) {
			l--;
			goto err_create_fdb;
		}

		fdb_prio_table(esw, chain, prio, l).fdb = fdb;
		fdb_prio_table(esw, chain, prio, l).num_rules = 1;
979
980
	}

981
982
	mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
	return fdb;
983

984
985
986
987
988
989
err_create_fdb:
	mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
	if (l >= 0)
		esw_put_prio_table(esw, chain, prio, l);

	return fdb;
990
991
}

992
993
static void
esw_put_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level)
994
{
995
996
	int l;

997
998
999
	if (chain == FDB_SLOW_PATH_CHAIN)
		return;

1000
	mutex_lock(&esw->fdb_table.offloads.fdb_prio_lock);