• Alan Kao's avatar
    perf: riscv: preliminary RISC-V support · 178e9fc4
    Alan Kao authored
    This patch provide a basic PMU, riscv_base_pmu, which supports two
    general hardware event, instructions and cycles.  Furthermore, this
    PMU serves as a reference implementation to ease the portings in
    the future.
    
    riscv_base_pmu should be able to run on any RISC-V machine that
    conforms to the Priv-Spec.  Note that the latest qemu model hasn't
    fully support a proper behavior of Priv-Spec 1.10 yet, but work
    around should be easy with very small fixes.  Please check
    https://github.com/riscv/riscv-qemu/pull/115
    
     for future updates.
    
    Cc: Nick Hu <nickhu@andestech.com>
    Cc: Greentime Hu <greentime@andestech.com>
    Signed-off-by: default avatarAlan Kao <alankao@andestech.com>
    Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
    178e9fc4
perf_event.c 11.3 KB