• Simon Guo's avatar
    KVM: PPC: Book3S PR: Add transaction memory save/restore skeleton · 8d2e2fc5
    Simon Guo authored
    The transaction memory checkpoint area save/restore behavior is
    triggered when VCPU qemu process is switching out/into CPU, i.e.
    at kvmppc_core_vcpu_put_pr() and kvmppc_core_vcpu_load_pr().
    MSR TM active state is determined by TS bits:
        active: 10(transactional) or 01 (suspended)
        inactive: 00 (non-transactional)
    We don't "fake" TM functionality for guest. We "sync" guest virtual
    MSR TM active state(10 or 01) with shadow MSR. That is to say,
    we don't emulate a transactional guest with a TM inactive MSR.
    TM SPR support(TFIAR/TFAR/TEXASR) has already been supported by
    commit 9916d57e
     ("KVM: PPC: Book3S PR: Expose TM registers").
    Math register support (FPR/VMX/VSX) will be done at subsequent
    Whether TM context need to be saved/restored can be determined
    by kvmppc_get_msr() TM active state:
    	* TM active - save/restore TM context
    	* TM inactive - no need to do so and only save/restore
    TM SPRs.
    Signed-off-by: default avatarSimon Guo <wei.guo.simon@gmail.com>
    Suggested-by: default avatarPaul Mackerras <paulus@ozlabs.org>
    Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>