Commit 0268099c authored by Gabriel FERNANDEZ's avatar Gabriel FERNANDEZ Committed by Mike Turquette
Browse files

clk: st: Update ST clock binding documentation



Naming convention was changed in dts file but the
clock binding documentation hasn't been updated.
Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin's avatarPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 381c1ccd
...@@ -24,26 +24,26 @@ Required properties: ...@@ -24,26 +24,26 @@ Required properties:
Example: Example:
clockgenA@fd345000 { clockgen-a@fd345000 {
reg = <0xfd345000 0xb50>; reg = <0xfd345000 0xb50>;
CLK_M_A1_DIV1: CLK_M_A1_DIV1 { clk_m_a1_div1: clk-m-a1-div1 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf1", compatible = "st,clkgena-divmux-c32-odf1",
"st,clkgena-divmux"; "st,clkgena-divmux";
clocks = <&CLK_M_A1_OSC_PREDIV>, clocks = <&clk_m_a1_osc_prediv>,
<&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */ <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
<&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */ <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
clock-output-names = "CLK_M_RX_ICN_TS", clock-output-names = "clk-m-rx-icn-ts",
"CLK_M_RX_ICN_VDP_0", "clk-m-rx-icn-vdp-0",
"", /* Unused */ "", /* unused */
"CLK_M_PRV_T1_BUS", "clk-m-prv-t1-bus",
"CLK_M_ICN_REG_12", "clk-m-icn-reg-12",
"CLK_M_ICN_REG_10", "clk-m-icn-reg-10",
"", /* Unused */ "", /* unused */
"CLK_M_ICN_ST231"; "clk-m-icn-st231";
}; };
}; };
...@@ -17,7 +17,7 @@ Required properties: ...@@ -17,7 +17,7 @@ Required properties:
"st,stih416-clkgenf-vcc-sd", "st,clkgen-mux" "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
"st,stih415-clkgen-a9-mux", "st,clkgen-mux" "st,stih415-clkgen-a9-mux", "st,clkgen-mux"
"st,stih416-clkgen-a9-mux", "st,clkgen-mux" "st,stih416-clkgen-a9-mux", "st,clkgen-mux"
"st,stih407-clkgen-a9-mux", "st,clkgen-mux"
- #clock-cells : from common clock binding; shall be set to 0. - #clock-cells : from common clock binding; shall be set to 0.
...@@ -27,10 +27,10 @@ Required properties: ...@@ -27,10 +27,10 @@ Required properties:
Example: Example:
CLK_M_HVA: CLK_M_HVA { clk_m_hva: clk-m-hva@fd690868 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"; compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
reg = <0xfd690868 4>; reg = <0xfd690868 4>;
clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>; clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
}; };
...@@ -19,11 +19,14 @@ Required properties: ...@@ -19,11 +19,14 @@ Required properties:
"st,stih415-plls-c32-ddr", "st,clkgen-plls-c32" "st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih416-plls-c32-a9", "st,clkgen-plls-c32" "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32" "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32" "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32" "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
- #clock-cells : From common clock binding; shall be set to 1. - #clock-cells : From common clock binding; shall be set to 1.
- clocks : From common clock binding - clocks : From common clock binding
...@@ -32,17 +35,17 @@ Required properties: ...@@ -32,17 +35,17 @@ Required properties:
Example: Example:
clockgenA@fee62000 { clockgen-a@fee62000 {
reg = <0xfee62000 0xb48>; reg = <0xfee62000 0xb48>;
CLK_S_A0_PLL: CLK_S_A0_PLL { clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,clkgena-plls-c65"; compatible = "st,clkgena-plls-c65";
clocks = <&CLK_SYSIN>; clocks = <&clk_sysin>;
clock-output-names = "CLK_S_A0_PLL0_HS", clock-output-names = "clk-s-a0-pll0-hs",
"CLK_S_A0_PLL0_LS", "clk-s-a0-pll0-ls",
"CLK_S_A0_PLL1"; "clk-s-a0-pll1";
}; };
}; };
...@@ -20,17 +20,17 @@ Required properties: ...@@ -20,17 +20,17 @@ Required properties:
Example: Example:
clockgenA@fd345000 { clockgen-a@fd345000 {
reg = <0xfd345000 0xb50>; reg = <0xfd345000 0xb50>;
CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV { clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "st,clkgena-prediv-c32", compatible = "st,clkgena-prediv-c32",
"st,clkgena-prediv"; "st,clkgena-prediv";
clocks = <&CLK_SYSIN>; clocks = <&clk_sysin>;
clock-output-names = "CLK_M_A2_OSC_PREDIV"; clock-output-names = "clk-m-a2-osc-prediv";
}; };
}; };
...@@ -32,22 +32,30 @@ Required properties: ...@@ -32,22 +32,30 @@ Required properties:
Example: Example:
CLOCKGEN_C_VCC: CLOCKGEN_C_VCC { clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih416-clkgenc", "st,clkgen-vcc"; compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
reg = <0xfe8308ac 12>; reg = <0xfe8308ac 12>;
clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>, clocks = <&clk_s_vcc_hd>,
<&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>; <&clockgen_c 1>,
<&clk_s_tmds_fromphy>,
clock-output-names = <&clockgen_c 2>;
"CLK_S_PIX_HDMI", "CLK_S_PIX_DVO",
"CLK_S_OUT_DVO", "CLK_S_PIX_HD", clock-output-names = "clk-s-pix-hdmi",
"CLK_S_HDDAC", "CLK_S_DENC", "clk-s-pix-dvo",
"CLK_S_SDDAC", "CLK_S_PIX_MAIN", "clk-s-out-dvo",
"CLK_S_PIX_AUX", "CLK_S_STFE_FRC_0", "clk-s-pix-hd",
"CLK_S_REF_MCRU", "CLK_S_SLAVE_MCRU", "clk-s-hddac",
"CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL", "clk-s-denc",
"CLK_S_THSENS"; "clk-s-sddac",
"clk-s-pix-main",
"clk-s-pix-aux",
"clk-s-stfe-frc-0",
"clk-s-ref-mcru",
"clk-s-slave-mcru",
"clk-s-tmds-hdmi",
"clk-s-hdmi-reject-pll",
"clk-s-thsens";
}; };
...@@ -24,60 +24,72 @@ address is common of all subnode. ...@@ -24,60 +24,72 @@ address is common of all subnode.
quadfs_node { quadfs_node {
... ...
}; };
mux_node {
...
};
vcc_node {
...
};
... ...
}; };
This binding uses the common clock binding[1]. This binding uses the common clock binding[1].
Each subnode should use the binding discribe in [2]..[4] Each subnode should use the binding discribe in [2]..[7]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st,quadfs.txt [2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
[3] Documentation/devicetree/bindings/clock/st,quadfs.txt [3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
[4] Documentation/devicetree/bindings/clock/st,quadfs.txt [4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
[6] Documentation/devicetree/bindings/clock/st,vcc.txt
[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
Required properties: Required properties:
- reg : A Base address and length of the register set. - reg : A Base address and length of the register set.
Example: Example:
clockgenA@fee62000 { clockgen-a@fee62000 {
reg = <0xfee62000 0xb48>; reg = <0xfee62000 0xb48>;
CLK_S_A0_PLL: CLK_S_A0_PLL { clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,clkgena-plls-c65"; compatible = "st,clkgena-plls-c65";
clocks = <&CLK_SYSIN>; clocks = <&clk-sysin>;
clock-output-names = "CLK_S_A0_PLL0_HS", clock-output-names = "clk-s-a0-pll0-hs",
"CLK_S_A0_PLL0_LS", "clk-s-a0-pll0-ls",
"CLK_S_A0_PLL1"; "clk-s-a0-pll1";
}; };
CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV { clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "st,clkgena-prediv-c65", compatible = "st,clkgena-prediv-c65",
"st,clkgena-prediv"; "st,clkgena-prediv";
clocks = <&CLK_SYSIN>; clocks = <&clk_sysin>;
clock-output-names = "CLK_S_A0_OSC_PREDIV"; clock-output-names = "clk-s-a0-osc-prediv";
}; };
CLK_S_A0_HS: CLK_S_A0_HS { clk_s_a0_hs: clk-s-a0-hs {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-hs", compatible = "st,clkgena-divmux-c65-hs",
"st,clkgena-divmux"; "st,clkgena-divmux";
clocks = <&CLK_S_A0_OSC_PREDIV>, clocks = <&clk-s_a0_osc_prediv>,
<&CLK_S_A0_PLL 0>, /* PLL0 HS */ <&clk-s_a0_pll 0>, /* pll0 hs */
<&CLK_S_A0_PLL 2>; /* PLL1 */ <&clk-s_a0_pll 2>; /* pll1 */
clock-output-names = "CLK_S_FDMA_0", clock-output-names = "clk-s-fdma-0",
"CLK_S_FDMA_1", "clk-s-fdma-1",
""; /* CLK_S_JIT_SENSE */ ""; /* clk-s-jit-sense */
/* Fourth output unused */ /* fourth output unused */
}; };
}; };
...@@ -15,6 +15,9 @@ Required properties: ...@@ -15,6 +15,9 @@ Required properties:
"st,stih416-quadfs432", "st,quadfs" "st,stih416-quadfs432", "st,quadfs"
"st,stih416-quadfs660-E", "st,quadfs" "st,stih416-quadfs660-E", "st,quadfs"
"st,stih416-quadfs660-F", "st,quadfs" "st,stih416-quadfs660-F", "st,quadfs"
"st,stih407-quadfs660-C", "st,quadfs"
"st,stih407-quadfs660-D", "st,quadfs"
- #clock-cells : from common clock binding; shall be set to 1. - #clock-cells : from common clock binding; shall be set to 1.
...@@ -32,14 +35,14 @@ Required properties: ...@@ -32,14 +35,14 @@ Required properties:
Example: Example:
CLOCKGEN_E: CLOCKGEN_E { clockgen_e: clockgen-e@fd3208bc {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih416-quadfs660-E", "st,quadfs"; compatible = "st,stih416-quadfs660-E", "st,quadfs";
reg = <0xfd3208bc 0xB0>; reg = <0xfd3208bc 0xB0>;
clocks = <&CLK_SYSIN>; clocks = <&clk_sysin>;
clock-output-names = "CLK_M_PIX_MDTP_0", clock-output-names = "clk-m-pix-mdtp-0",
"CLK_M_PIX_MDTP_1", "clk-m-pix-mdtp-1",
"CLK_M_PIX_MDTP_2", "clk-m-pix-mdtp-2",
"CLK_M_MPELPC"; "clk-m-mpelpc";
}; };
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