Commit 3db385ea authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung into clk-next

Pull samsung clk driver updates from Sylwester Nawrocki:

In addition to a few clean up and code consolidation patches this
includes:
- addition of sound subsystem related clocks for Exynos5410 SoC
  (EPLL, PDMA) and support for "samsung,exynos5410-audss-clock"
  compatible in the clk-exynos-audss driver,
- addition of DRAM controller related clocks for exynos5420,
- MAINTAINERS update adding Chanwoo Choi as the Samsung SoC
  clock drivers co-maintainer.

* tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung:
  clk: samsung: Add support for EPLL on exynos5410
  clk: samsung: clk-exynos-audss: Whitespace and debug trace cleanup
  clk: samsung: clk-exynos-audss: Add exynos5410 compatible
  clk: samsung: clk-exynos-audss: controller variant handling rework
  clk: samsung: Use common registration function for pll2550x
  clk: samsung: exynos5410: Expose the peripheral DMA gate clocks
  clk: samsung: exynos5420: Add clocks for CMU_CDREX domain
  clk: samsung: exynos5410: Use samsung_cmu_register_one() to simplify code
  clk: samsung: exynos5260: Move struct samsung_cmu_info to init section
  MAINTAINERS: Add myself as Samsung SoC clock drivers co-maintainer
  clk: samsung: exynos5410: Add clock IDs for PDMA and EPLL clocks
  clk: samsung: Add clock IDs for the CMU_CDREX (DRAM Express Controller)
parents 7348b6ce be95d2c7
......@@ -10,6 +10,8 @@ Required Properties:
- "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
- "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
SoCs.
- "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410
SoCs.
- "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
SoCs.
- reg: physical base address and length of the controller's register set.
......@@ -91,5 +93,5 @@ i2s0: i2s@03830000 {
<&clock_audss EXYNOS_MOUT_AUDSS>,
<&clock_audss EXYNOS_MOUT_I2S>;
clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
"mout_audss", "mout_i2s";
"mout_audss", "mout_i2s";
};
......@@ -12,24 +12,29 @@ Required Properties:
- #clock-cells: should be 1.
- clocks: should contain an entry specifying the root clock from external
oscillator supplied through XXTI or XusbXTI pin. This clock should be
defined using standard clock bindings with "fin_pll" clock-output-name.
That clock is being passed internally to the 9 PLLs.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos5410.h header and can be used in device
tree sources.
External clock:
There is clock that is generated outside the SoC. It
is expected that it is defined using standard clock bindings
with following clock-output-name:
- "fin_pll" - PLL input clock from XXTI
Example 1: An example of a clock controller node is listed below.
fin_pll: xxti {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "fin_pll";
#clock-cells = <0>;
};
clock: clock-controller@0x10010000 {
compatible = "samsung,exynos5410-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
clocks = <&fin_pll>;
};
Example 2: UART controller node that consumes the clock generated by the clock
......
......@@ -10240,9 +10240,12 @@ F: drivers/nfc/s3fwrn5
SAMSUNG SOC CLOCK DRIVERS
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
M: Tomasz Figa <tomasz.figa@gmail.com>
M: Chanwoo Choi <cw00.choi@samsung.com>
S: Supported
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
F: drivers/clk/samsung/
F: include/dt-bindings/clock/exynos*.h
F: Documentation/devicetree/bindings/clock/exynos*.txt
SAMSUNG SXGBE DRIVERS
M: Byungho An <bh74.an@samsung.com>
......
......@@ -14,18 +14,13 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/syscore_ops.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/exynos-audss-clk.h>
enum exynos_audss_clk_type {
TYPE_EXYNOS4210,
TYPE_EXYNOS5250,
TYPE_EXYNOS5420,
};
static DEFINE_SPINLOCK(lock);
static struct clk **clk_table;
static void __iomem *reg_base;
......@@ -44,9 +39,9 @@ static struct clk *epll;
#ifdef CONFIG_PM_SLEEP
static unsigned long reg_save[][2] = {
{ASS_CLK_SRC, 0},
{ASS_CLK_DIV, 0},
{ASS_CLK_GATE, 0},
{ ASS_CLK_SRC, 0 },
{ ASS_CLK_DIV, 0 },
{ ASS_CLK_GATE, 0 },
};
static int exynos_audss_clk_suspend(void)
......@@ -73,14 +68,43 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
};
#endif /* CONFIG_PM_SLEEP */
struct exynos_audss_clk_drvdata {
unsigned int has_adma_clk:1;
unsigned int has_mst_clk:1;
unsigned int enable_epll:1;
unsigned int num_clks;
};
static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
.num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
};
static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
.num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
.has_mst_clk = 1,
};
static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
.num_clks = EXYNOS_AUDSS_MAX_CLKS,
.has_adma_clk = 1,
.enable_epll = 1,
};
static const struct of_device_id exynos_audss_clk_of_match[] = {
{ .compatible = "samsung,exynos4210-audss-clock",
.data = (void *)TYPE_EXYNOS4210, },
{ .compatible = "samsung,exynos5250-audss-clock",
.data = (void *)TYPE_EXYNOS5250, },
{ .compatible = "samsung,exynos5420-audss-clock",
.data = (void *)TYPE_EXYNOS5420, },
{},
{
.compatible = "samsung,exynos4210-audss-clock",
.data = &exynos4210_drvdata,
}, {
.compatible = "samsung,exynos5250-audss-clock",
.data = &exynos4210_drvdata,
}, {
.compatible = "samsung,exynos5410-audss-clock",
.data = &exynos5410_drvdata,
}, {
.compatible = "samsung,exynos5420-audss-clock",
.data = &exynos5420_drvdata,
},
{ },
};
static void exynos_audss_clk_teardown(void)
......@@ -106,19 +130,17 @@ static void exynos_audss_clk_teardown(void)
/* register exynos_audss clocks */
static int exynos_audss_clk_probe(struct platform_device *pdev)
{
int i, ret = 0;
struct resource *res;
const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
const char *sclk_pcm_p = "sclk_pcm0";
struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
const struct of_device_id *match;
enum exynos_audss_clk_type variant;
const struct exynos_audss_clk_drvdata *variant;
struct resource *res;
int i, ret = 0;
match = of_match_node(exynos_audss_clk_of_match, pdev->dev.of_node);
if (!match)
variant = of_device_get_match_data(&pdev->dev);
if (!variant)
return -EINVAL;
variant = (enum exynos_audss_clk_type)match->data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
reg_base = devm_ioremap_resource(&pdev->dev, res);
......@@ -126,7 +148,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "failed to map audss registers\n");
return PTR_ERR(reg_base);
}
/* EPLL don't have to be enabled for boards other than Exynos5420 */
epll = ERR_PTR(-ENODEV);
clk_table = devm_kzalloc(&pdev->dev,
......@@ -136,10 +158,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
return -ENOMEM;
clk_data.clks = clk_table;
if (variant == TYPE_EXYNOS5420)
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
else
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
clk_data.clk_num = variant->num_clks;
pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
pll_in = devm_clk_get(&pdev->dev, "pll_in");
......@@ -148,13 +167,13 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
if (!IS_ERR(pll_in)) {
mout_audss_p[1] = __clk_get_name(pll_in);
if (variant == TYPE_EXYNOS5420) {
if (variant->enable_epll) {
epll = pll_in;
ret = clk_prepare_enable(epll);
if (ret) {
dev_err(&pdev->dev,
"failed to prepare the epll clock\n");
"failed to prepare the epll clock\n");
return ret;
}
}
......@@ -210,7 +229,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
sclk_pcm_p, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, &lock);
if (variant == TYPE_EXYNOS5420) {
if (variant->has_adma_clk) {
clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
"dout_srp", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 9, 0, &lock);
......@@ -234,9 +253,6 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(&exynos_audss_clk_syscore_ops);
#endif
dev_info(&pdev->dev, "setup completed\n");
return 0;
unregister:
......
......@@ -131,21 +131,21 @@ static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
EN_IP_AUD, 4, 0, 0),
};
static const struct samsung_cmu_info aud_cmu __initconst = {
.mux_clks = aud_mux_clks,
.nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
.div_clks = aud_div_clks,
.nr_div_clks = ARRAY_SIZE(aud_div_clks),
.gate_clks = aud_gate_clks,
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
.nr_clk_ids = AUD_NR_CLK,
.clk_regs = aud_clk_regs,
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
};
static void __init exynos5260_clk_aud_init(struct device_node *np)
{
struct samsung_cmu_info cmu = { NULL };
cmu.mux_clks = aud_mux_clks;
cmu.nr_mux_clks = ARRAY_SIZE(aud_mux_clks);
cmu.div_clks = aud_div_clks;
cmu.nr_div_clks = ARRAY_SIZE(aud_div_clks);
cmu.gate_clks = aud_gate_clks;
cmu.nr_gate_clks = ARRAY_SIZE(aud_gate_clks);
cmu.nr_clk_ids = AUD_NR_CLK;
cmu.clk_regs = aud_clk_regs;
cmu.nr_clk_regs = ARRAY_SIZE(aud_clk_regs);
samsung_cmu_register_one(np, &cmu);
samsung_cmu_register_one(np, &aud_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",
......@@ -321,21 +321,21 @@ static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
EN_IP_DISP, 25, 0, 0),
};
static const struct samsung_cmu_info disp_cmu __initconst = {
.mux_clks = disp_mux_clks,
.nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
.div_clks = disp_div_clks,
.nr_div_clks = ARRAY_SIZE(disp_div_clks),
.gate_clks = disp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
.nr_clk_ids = DISP_NR_CLK,
.clk_regs = disp_clk_regs,
.nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
};
static void __init exynos5260_clk_disp_init(struct device_node *np)
{
struct samsung_cmu_info cmu = { NULL };
cmu.mux_clks = disp_mux_clks;
cmu.nr_mux_clks = ARRAY_SIZE(disp_mux_clks);
cmu.div_clks = disp_div_clks;
cmu.nr_div_clks = ARRAY_SIZE(disp_div_clks);
cmu.gate_clks = disp_gate_clks;
cmu.nr_gate_clks = ARRAY_SIZE(disp_gate_clks);
cmu.nr_clk_ids = DISP_NR_CLK;
cmu.clk_regs = disp_clk_regs;
cmu.nr_clk_regs = ARRAY_SIZE(disp_clk_regs);
samsung_cmu_register_one(np, &cmu);
samsung_cmu_register_one(np, &disp_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",
......@@ -385,21 +385,21 @@ static const struct samsung_pll_clock egl_pll_clks[] __initconst = {
pll2550_24mhz_tbl),
};
static const struct samsung_cmu_info egl_cmu __initconst = {
.pll_clks = egl_pll_clks,
.nr_pll_clks = ARRAY_SIZE(egl_pll_clks),
.mux_clks = egl_mux_clks,
.nr_mux_clks = ARRAY_SIZE(egl_mux_clks),
.div_clks = egl_div_clks,
.nr_div_clks = ARRAY_SIZE(egl_div_clks),
.nr_clk_ids = EGL_NR_CLK,
.clk_regs = egl_clk_regs,
.nr_clk_regs = ARRAY_SIZE(egl_clk_regs),
};
static void __init exynos5260_clk_egl_init(struct device_node *np)
{
struct samsung_cmu_info cmu = { NULL };
cmu.pll_clks = egl_pll_clks;
cmu.nr_pll_clks = ARRAY_SIZE(egl_pll_clks);
cmu.mux_clks = egl_mux_clks;
cmu.nr_mux_clks = ARRAY_SIZE(egl_mux_clks);
cmu.div_clks = egl_div_clks;
cmu.nr_div_clks = ARRAY_SIZE(egl_div_clks);
cmu.nr_clk_ids = EGL_NR_CLK;
cmu.clk_regs = egl_clk_regs;
cmu.nr_clk_regs = ARRAY_SIZE(egl_clk_regs);
samsung_cmu_register_one(np, &cmu);
samsung_cmu_register_one(np, &egl_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",
......@@ -487,19 +487,19 @@ static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
EN_IP_FSYS_SECURE_SMMU_RTIC, 12, 0, 0),
};
static const struct samsung_cmu_info fsys_cmu __initconst = {
.mux_clks = fsys_mux_clks,
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
.gate_clks = fsys_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
.nr_clk_ids = FSYS_NR_CLK,
.clk_regs = fsys_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
};
static void __init exynos5260_clk_fsys_init(struct device_node *np)
{
struct samsung_cmu_info cmu = { NULL };
cmu.mux_clks = fsys_mux_clks;
cmu.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks);
cmu.gate_clks = fsys_gate_clks;
cmu.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks);
cmu.nr_clk_ids = FSYS_NR_CLK;
cmu.clk_regs = fsys_clk_regs;
cmu.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs);
samsung_cmu_register_one(np, &cmu);
samsung_cmu_register_one(np, &fsys_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",
......@@ -576,21 +576,21 @@ static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
EN_IP_G2D_SECURE_SMMU_G2D, 15, 0, 0),
};
static const struct samsung_cmu_info g2d_cmu __initconst = {
.mux_clks = g2d_mux_clks,
.nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
.div_clks = g2d_div_clks,
.nr_div_clks = ARRAY_SIZE(g2d_div_clks),
.gate_clks = g2d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
.nr_clk_ids = G2D_NR_CLK,
.clk_regs = g2d_clk_regs,
.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
};
static void __init exynos5260_clk_g2d_init(struct device_node *np)
{
struct samsung_cmu_info cmu = { NULL };
cmu.mux_clks = g2d_mux_clks;
cmu.nr_mux_clks = ARRAY_SIZE(g2d_mux_clks);
cmu.div_clks = g2d_div_clks;
cmu.nr_div_clks = ARRAY_SIZE(g2d_div_clks);
cmu.gate_clks = g2d_gate_clks;
cmu.nr_gate_clks = ARRAY_SIZE(g2d_gate_clks);
cmu.nr_clk_ids = G2D_NR_CLK;
cmu.clk_regs = g2d_clk_regs;
cmu.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs);
samsung_cmu_register_one(np, &cmu);
samsung_cmu_register_one(np, &g2d_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",
......@@ -637,23 +637,23 @@ static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
pll2550_24mhz_tbl),
};
static const struct samsung_cmu_info g3d_cmu __initconst = {
.pll_clks = g3d_pll_clks,
.nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
.mux_clks = g3d_mux_clks,
.nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
.div_clks = g3d_div_clks,
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
.gate_clks = g3d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
.nr_clk_ids = G3D_NR_CLK,
.clk_regs = g3d_clk_regs,
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
};
static void __init exynos5260_clk_g3d_init(struct device_node *np)
{
struct samsung_cmu_info cmu = { NULL };
cmu.pll_clks = g3d_pll_clks;
cmu.nr_pll_clks = ARRAY_SIZE(g3d_pll_clks);
cmu.mux_clks = g3d_mux_clks;
cmu.nr_mux_clks = ARRAY_SIZE(g3d_mux_clks);
cmu.div_clks = g3d_div_clks;
cmu.nr_div_clks = ARRAY_SIZE(g3d_div_clks);
cmu.gate_clks = g3d_gate_clks;
cmu.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks);
cmu.nr_clk_ids = G3D_NR_CLK;
cmu.clk_regs = g3d_clk_regs;
cmu.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs);
samsung_cmu_register_one(np, &cmu);
samsung_cmu_register_one(np, &g3d_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",
......@@ -772,21 +772,21 @@ static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
EN_IP_GSCL_SECURE_SMMU_MSCL1, 20, 0, 0),
};
static const struct samsung_cmu_info gscl_cmu __initconst = {
.mux_clks = gscl_mux_clks,
.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
.div_clks = gscl_div_clks,
.nr_div_clks = ARRAY_SIZE(gscl_div_clks),
.gate_clks = gscl_gate_clks,
.nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
.nr_clk_ids = GSCL_NR_CLK,
.clk_regs = gscl_clk_regs,
.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
};
static void __init exynos5260_clk_gscl_init(struct device_node *np)
{
struct samsung_cmu_info cmu = { NULL };
cmu.mux_clks = gscl_mux_clks;
cmu.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks);
cmu.div_clks = gscl_div_clks;
cmu.nr_div_clks = ARRAY_SIZE(gscl_div_clks);
cmu.gate_clks = gscl_gate_clks;
cmu.nr_gate_clks = ARRAY_SIZE(gscl_gate_clks);
cmu.nr_clk_ids = GSCL_NR_CLK;
cmu.clk_regs = gscl_clk_regs;
cmu.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs);
samsung_cmu_register_one(np, &cmu);
samsung_cmu_register_one(np, &gscl_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",
......@@ -891,21 +891,21 @@ static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
EN_SCLK_ISP, 9, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_cmu_info isp_cmu __initconst = {
.mux_clks = isp_mux_clks,
.nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
.div_clks = isp_div_clks,
.nr_div_clks = ARRAY_SIZE(isp_div_clks),
.gate_clks = isp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
.nr_clk_ids = ISP_NR_CLK,
.clk_regs = isp_clk_regs,
.nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
};
static void __init exynos5260_clk_isp_init(struct device_node *np)
{
struct samsung_cmu_info cmu = { NULL };
cmu.mux_clks = isp_mux_clks;
cmu.nr_mux_clks = ARRAY_SIZE(isp_mux_clks);
cmu.div_clks = isp_div_clks;
cmu.nr_div_clks = ARRAY_SIZE(isp_div_clks);
cmu.gate_clks = isp_gate_clks;
cmu.nr_gate_clks = ARRAY_SIZE(isp_gate_clks);
cmu.nr_clk_ids = ISP_NR_CLK;
cmu.clk_regs = isp_clk_regs;
cmu.nr_clk_regs = ARRAY_SIZE(isp_clk_regs);
samsung_cmu_register_one(np, &cmu);
samsung_cmu_register_one(np, &isp_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",
......@@ -955,21 +955,21 @@ static const struct samsung_pll_clock kfc_pll_clks[] __initconst = {
pll2550_24mhz_tbl),
};
static const struct samsung_cmu_info kfc_cmu __initconst = {
.pll_clks = kfc_pll_clks,
.nr_pll_clks = ARRAY_SIZE(kfc_pll_clks),
.mux_clks = kfc_mux_clks,
.nr_mux_clks = ARRAY_SIZE(kfc_mux_clks),
.div_clks = kfc_div_clks,
.nr_div_clks = ARRAY_SIZE(kfc_div_clks),
.nr_clk_ids = KFC_NR_CLK,
.clk_regs = kfc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(kfc_clk_regs),
};
static void __init exynos5260_clk_kfc_init(struct device_node *np)
{
struct samsung_cmu_info cmu = { NULL };
cmu.pll_clks = kfc_pll_clks;
cmu.nr_pll_clks = ARRAY_SIZE(kfc_pll_clks);
cmu.mux_clks = kfc_mux_clks;
cmu.nr_mux_clks = ARRAY_SIZE(kfc_mux_clks);
cmu.div_clks = kfc_div_clks;
cmu.nr_div_clks = ARRAY_SIZE(kfc_div_clks);
cmu.nr_clk_ids = KFC_NR_CLK;
cmu.clk_regs = kfc_clk_regs;
cmu.nr_clk_regs = ARRAY_SIZE(kfc_clk_regs);
samsung_cmu_register_one(np, &cmu);
samsung_cmu_register_one(np, &kfc_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",
......@@ -1011,21 +1011,21 @@ static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
EN_IP_MFC_SECURE_SMMU2_MFC, 7, 0, 0),
};
static const struct samsung_cmu_info mfc_cmu __initconst = {
.mux_clks = mfc_mux_clks,
.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
.div_clks = mfc_div_clks,
.nr_div_clks = ARRAY_SIZE(mfc_div_clks),
.gate_clks = mfc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
.nr_clk_ids = MFC_NR_CLK,
.clk_regs = mfc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
};
static void __init exynos5260_clk_mfc_init(struct device_node *np)
{
struct samsung_cmu_info cmu = { NULL };
cmu.mux_clks = mfc_mux_clks;
cmu.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks);
cmu.div_clks = mfc_div_clks;
cmu.nr_div_clks = ARRAY_SIZE(mfc_div_clks);
cmu.gate_clks = mfc_gate_clks;
cmu.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks);
cmu.nr_clk_ids = MFC_NR_CLK;
cmu.clk_regs = mfc_clk_regs;
cmu.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs);
samsung_cmu_register_one(np, &cmu);
samsung_cmu_register_one(np, &mfc_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",
......@@ -1158,23 +1158,23 @@ static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
pll2550_24mhz_tbl),
};
static const struct samsung_cmu_info mif_cmu __initconst = {
.pll_clks = mif_pll_clks,
.nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
.mux_clks = mif_mux_clks,
.nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
.div_clks = mif_div_clks,
.nr_div_clks = ARRAY_SIZE(mif_div_clks),
.gate_clks = mif_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
.nr_clk_ids = MIF_NR_CLK,
.clk_regs = mif_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
};
static void __init exynos5260_clk_mif_init(struct device_node *np)
{
struct samsung_cmu_info cmu = { NULL };
cmu.pll_clks = mif_pll_clks;
cmu.nr_pll_clks = ARRAY_SIZE(mif_pll_clks);
cmu.mux_clks = mif_mux_clks;
cmu.nr_mux_clks = ARRAY_SIZE(mif_mux_clks);
cmu.div_clks = mif_div_clks;
cmu.nr_div_clks = ARRAY_SIZE(mif_div_clks);
cmu.gate_clks = mif_gate_clks;
cmu.nr_gate_clks = ARRAY_SIZE(mif_gate_clks);
cmu.nr_clk_ids = MIF_NR_CLK;