Commit 880d54ff authored by Gabriel Fernandez's avatar Gabriel Fernandez Committed by Stephen Boyd
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drivers: clk: st: Simplify clock binding of STiH4xx platforms

This patch reworks the clock binding to avoid too much detail in DT.
Now we have only compatible string per type of clock
(remark from Rob https://lkml.org/lkml/2016/5/25/492

)
Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Peter Griffin's avatarPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 7df404c9
...@@ -10,7 +10,7 @@ This binding uses the common clock binding[1]. ...@@ -10,7 +10,7 @@ This binding uses the common clock binding[1].
Required properties: Required properties:
- compatible : shall be: - compatible : shall be:
"st,stih407-clkgen-a9-mux", "st,clkgen-mux" "st,stih407-clkgen-a9-mux"
- #clock-cells : from common clock binding; shall be set to 0. - #clock-cells : from common clock binding; shall be set to 0.
......
...@@ -9,11 +9,10 @@ Base address is located to the parent node. See clock binding[2] ...@@ -9,11 +9,10 @@ Base address is located to the parent node. See clock binding[2]
Required properties: Required properties:
- compatible : shall be: - compatible : shall be:
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32" "st,clkgen-pll0"
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32" "st,clkgen-pll1"
"sst,plls-c32-cx_0", "st,clkgen-plls-c32" "st,stih407-clkgen-plla9"
"sst,plls-c32-cx_1", "st,clkgen-plls-c32" "st,stih418-clkgen-plla9"
"st,stih418-plls-c28-a9", "st,clkgen-plls-c32"
- #clock-cells : From common clock binding; shall be set to 1. - #clock-cells : From common clock binding; shall be set to 1.
...@@ -29,7 +28,7 @@ Example: ...@@ -29,7 +28,7 @@ Example:
clockgen_a9_pll: clockgen-a9-pll { clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; compatible = "st,stih407-clkgen-plla9";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
......
...@@ -48,7 +48,7 @@ Example: ...@@ -48,7 +48,7 @@ Example:
clk_s_a0_pll: clk-s-a0-pll { clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; compatible = "st,clkgen-pll0";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
......
...@@ -11,8 +11,8 @@ This binding uses the common clock binding[1]. ...@@ -11,8 +11,8 @@ This binding uses the common clock binding[1].
Required properties: Required properties:
- compatible : shall be: - compatible : shall be:
"st,stih407-quadfs660-C", "st,quadfs" "st,quadfs"
"st,stih407-quadfs660-D", "st,quadfs" "st,quadfs-pll"
- #clock-cells : from common clock binding; shall be set to 1. - #clock-cells : from common clock binding; shall be set to 1.
...@@ -33,7 +33,7 @@ Example: ...@@ -33,7 +33,7 @@ Example:
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-quadfs660-C", "st,quadfs"; compatible = "st,quadfs-pll";
reg = <0x9103000 0x1000>; reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
......
...@@ -819,18 +819,6 @@ static struct clk * __init st_clk_register_quadfs_fsynth( ...@@ -819,18 +819,6 @@ static struct clk * __init st_clk_register_quadfs_fsynth(
return clk; return clk;
} }
static const struct of_device_id quadfs_of_match[] = {
{
.compatible = "st,stih407-quadfs660-C",
.data = &st_fs660c32_C
},
{
.compatible = "st,stih407-quadfs660-D",
.data = &st_fs660c32_D
},
{}
};
static void __init st_of_create_quadfs_fsynths( static void __init st_of_create_quadfs_fsynths(
struct device_node *np, const char *pll_name, struct device_node *np, const char *pll_name,
struct clkgen_quadfs_data *quadfs, void __iomem *reg, struct clkgen_quadfs_data *quadfs, void __iomem *reg,
...@@ -890,18 +878,14 @@ static void __init st_of_create_quadfs_fsynths( ...@@ -890,18 +878,14 @@ static void __init st_of_create_quadfs_fsynths(
of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
} }
static void __init st_of_quadfs_setup(struct device_node *np) static void __init st_of_quadfs_setup(struct device_node *np,
struct clkgen_quadfs_data *data)
{ {
const struct of_device_id *match;
struct clk *clk; struct clk *clk;
const char *pll_name, *clk_parent_name; const char *pll_name, *clk_parent_name;
void __iomem *reg; void __iomem *reg;
spinlock_t *lock; spinlock_t *lock;
match = of_match_node(quadfs_of_match, np);
if (WARN_ON(!match))
return;
reg = of_iomap(np, 0); reg = of_iomap(np, 0);
if (!reg) if (!reg)
return; return;
...@@ -920,8 +904,8 @@ static void __init st_of_quadfs_setup(struct device_node *np) ...@@ -920,8 +904,8 @@ static void __init st_of_quadfs_setup(struct device_node *np)
spin_lock_init(lock); spin_lock_init(lock);
clk = st_clk_register_quadfs_pll(pll_name, clk_parent_name, clk = st_clk_register_quadfs_pll(pll_name, clk_parent_name, data,
(struct clkgen_quadfs_data *) match->data, reg, lock); reg, lock);
if (IS_ERR(clk)) if (IS_ERR(clk))
goto err_exit; goto err_exit;
else else
...@@ -930,11 +914,20 @@ static void __init st_of_quadfs_setup(struct device_node *np) ...@@ -930,11 +914,20 @@ static void __init st_of_quadfs_setup(struct device_node *np)
__clk_get_name(clk_get_parent(clk)), __clk_get_name(clk_get_parent(clk)),
(unsigned int)clk_get_rate(clk)); (unsigned int)clk_get_rate(clk));
st_of_create_quadfs_fsynths(np, pll_name, st_of_create_quadfs_fsynths(np, pll_name, data, reg, lock);
(struct clkgen_quadfs_data *)match->data,
reg, lock);
err_exit: err_exit:
kfree(pll_name); /* No longer need local copy of the PLL name */ kfree(pll_name); /* No longer need local copy of the PLL name */
} }
CLK_OF_DECLARE(quadfs, "st,quadfs", st_of_quadfs_setup);
static void __init st_of_quadfs660C_setup(struct device_node *np)
{
st_of_quadfs_setup(np, (struct clkgen_quadfs_data *) &st_fs660c32_C);
}
CLK_OF_DECLARE(quadfs660C, "st,quadfs-pll", st_of_quadfs660C_setup);
static void __init st_of_quadfs660D_setup(struct device_node *np)
{
st_of_quadfs_setup(np, (struct clkgen_quadfs_data *) &st_fs660c32_D);
}
CLK_OF_DECLARE(quadfs660D, "st,quadfs", st_of_quadfs660D_setup);
...@@ -53,29 +53,13 @@ static struct clkgen_mux_data stih407_a9_mux_data = { ...@@ -53,29 +53,13 @@ static struct clkgen_mux_data stih407_a9_mux_data = {
.lock = &clkgen_a9_lock, .lock = &clkgen_a9_lock,
}; };
static const struct of_device_id mux_of_match[] = { static void __init st_of_clkgen_mux_setup(struct device_node *np,
{ struct clkgen_mux_data *data)
.compatible = "st,stih407-clkgen-a9-mux",
.data = &stih407_a9_mux_data,
},
{}
};
static void __init st_of_clkgen_mux_setup(struct device_node *np)
{ {
const struct of_device_id *match;
struct clk *clk; struct clk *clk;
void __iomem *reg; void __iomem *reg;
const char **parents; const char **parents;
int num_parents = 0; int num_parents = 0;
const struct clkgen_mux_data *data;
match = of_match_node(mux_of_match, np);
if (!match) {
pr_err("%s: No matching data\n", __func__);
return;
}
data = match->data;
reg = of_iomap(np, 0); reg = of_iomap(np, 0);
if (!reg) { if (!reg) {
...@@ -112,4 +96,10 @@ err: ...@@ -112,4 +96,10 @@ err:
err_parents: err_parents:
iounmap(reg); iounmap(reg);
} }
CLK_OF_DECLARE(clkgen_mux, "st,clkgen-mux", st_of_clkgen_mux_setup);
static void __init st_of_clkgen_a9_mux_setup(struct device_node *np)
{
st_of_clkgen_mux_setup(np, &stih407_a9_mux_data);
}
CLK_OF_DECLARE(clkgen_a9mux, "st,stih407-clkgen-a9-mux",
st_of_clkgen_a9_mux_setup);
...@@ -702,48 +702,17 @@ static struct clk * __init clkgen_odf_register(const char *parent_name, ...@@ -702,48 +702,17 @@ static struct clk * __init clkgen_odf_register(const char *parent_name,
return clk; return clk;
} }
static const struct of_device_id c32_pll_of_match[] = {
{
.compatible = "st,stih407-plls-c32-a0",
.data = &st_pll3200c32_407_a0,
},
{
.compatible = "st,plls-c32-cx_0",
.data = &st_pll3200c32_cx_0,
},
{
.compatible = "st,plls-c32-cx_1",
.data = &st_pll3200c32_cx_1,
},
{
.compatible = "st,stih407-plls-c32-a9",
.data = &st_pll3200c32_407_a9,
},
{
.compatible = "st,stih418-plls-c28-a9",
.data = &st_pll4600c28_418_a9,
},
{}
};
static void __init clkgen_c32_pll_setup(struct device_node *np) static void __init clkgen_c32_pll_setup(struct device_node *np,
struct clkgen_pll_data *data)
{ {
const struct of_device_id *match;
struct clk *clk; struct clk *clk;
const char *parent_name, *pll_name; const char *parent_name, *pll_name;
void __iomem *pll_base; void __iomem *pll_base;
int num_odfs, odf; int num_odfs, odf;
struct clk_onecell_data *clk_data; struct clk_onecell_data *clk_data;
struct clkgen_pll_data *data;
unsigned long pll_flags = 0; unsigned long pll_flags = 0;
match = of_match_node(c32_pll_of_match, np);
if (!match) {
pr_err("%s: No matching data\n", __func__);
return;
}
data = (struct clkgen_pll_data *) match->data;
parent_name = of_clk_get_parent_name(np, 0); parent_name = of_clk_get_parent_name(np, 0);
if (!parent_name) if (!parent_name)
...@@ -802,4 +771,30 @@ err: ...@@ -802,4 +771,30 @@ err:
kfree(clk_data->clks); kfree(clk_data->clks);
kfree(clk_data); kfree(clk_data);
} }
CLK_OF_DECLARE(clkgen_c32_pll, "st,clkgen-plls-c32", clkgen_c32_pll_setup); static void __init clkgen_c32_pll0_setup(struct device_node *np)
{
clkgen_c32_pll_setup(np,
(struct clkgen_pll_data *) &st_pll3200c32_cx_0);
}
CLK_OF_DECLARE(c32_pll0, "st,clkgen-pll0", clkgen_c32_pll0_setup);
static void __init clkgen_c32_pll1_setup(struct device_node *np)
{
clkgen_c32_pll_setup(np,
(struct clkgen_pll_data *) &st_pll3200c32_cx_1);
}
CLK_OF_DECLARE(c32_pll1, "st,clkgen-pll1", clkgen_c32_pll1_setup);
static void __init clkgen_c32_plla9_setup(struct device_node *np)
{
clkgen_c32_pll_setup(np,
(struct clkgen_pll_data *) &st_pll3200c32_407_a9);
}
CLK_OF_DECLARE(c32_plla9, "st,stih407-clkgen-plla9", clkgen_c32_plla9_setup);
static void __init clkgen_c28_plla9_setup(struct device_node *np)
{
clkgen_c32_pll_setup(np,
(struct clkgen_pll_data *) &st_pll4600c28_418_a9);
}
CLK_OF_DECLARE(c28_plla9, "st,stih418-clkgen-plla9", clkgen_c28_plla9_setup);
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