Commit 964e3717 authored by Stephen Boyd's avatar Stephen Boyd
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Merge tag 'clk-renesas-for-v4.19-tag1' of...

Merge tag 'clk-renesas-for-v4.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates for v4.19 from Geert Uytterhoeven:

  - Add support for Crypto Engine clocks on R-Car H3
  - Add support for the new RZ/N1D SoC

* tag 'clk-renesas-for-v4.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: Renesas R9A06G032 clock driver
  dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation
  dt-bindings: clock: Add the r9a06g032-sysctrl.h file
  clk: renesas: r8a7795: Add CCREE clock
  clk: renesas: r8a7795: Add CR clock
parents ce397d21 4c3d8852
* Renesas R9A06G032 SYSCTRL
Required Properties:
- compatible: Must be:
- "renesas,r9a06g032-sysctrl"
- reg: Base address and length of the SYSCTRL IO block.
- #clock-cells: Must be 1
- clocks: References to the parent clocks:
- external 40mhz crystal.
- external (optional) 32.768khz
- external (optional) jtag input
- external (optional) RGMII_REFCLK
- clock-names: Must be:
clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
Examples
--------
- SYSCTRL node:
sysctrl: system-controller@4000c000 {
compatible = "renesas,r9a06g032-sysctrl";
reg = <0x4000c000 0x1000>;
#clock-cells = <1>;
clocks = <&ext_mclk>, <&ext_rtc_clk>,
<&ext_jtag_clk>, <&ext_rgmii_ref>;
clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
};
- Other nodes can use the clocks provided by SYSCTRL as in:
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
uart0: serial@40060000 {
compatible = "snps,dw-apb-uart";
reg = <0x40060000 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART0>;
clock-names = "baudclk";
};
......@@ -21,6 +21,7 @@ config CLK_RENESAS
select CLK_R8A77980 if ARCH_R8A77980
select CLK_R8A77990 if ARCH_R8A77990
select CLK_R8A77995 if ARCH_R8A77995
select CLK_R9A06G032 if ARCH_R9A06G032
select CLK_SH73A0 if ARCH_SH73A0
if CLK_RENESAS
......@@ -125,6 +126,11 @@ config CLK_R8A77995
bool "R-Car D3 clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
config CLK_R9A06G032
bool "Renesas R9A06G032 clock driver"
help
This is a driver for R9A06G032 clocks
config CLK_SH73A0
bool "SH-Mobile AG5 clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSTP
......
......@@ -20,6 +20,7 @@ obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
# Family
......
......@@ -103,6 +103,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
......@@ -132,6 +133,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
DEF_MOD("cmt3", 300, R8A7795_CLK_R),
DEF_MOD("cmt2", 301, R8A7795_CLK_R),
DEF_MOD("cmt1", 302, R8A7795_CLK_R),
......
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0 */
/*
* R9A06G032 sysctrl IDs
*
* Copyright (C) 2018 Renesas Electronics Europe Limited
*
* Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
*/
#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__
#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__
#define R9A06G032_CLK_PLL_USB 1
#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */
#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */
#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */
#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */
#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */
#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */
#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */
#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */
#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */
#define R9A06G032_CLK_25_PG4 26
#define R9A06G032_CLK_25_PG5 27
#define R9A06G032_CLK_25_PG6 28
#define R9A06G032_CLK_25_PG7 29
#define R9A06G032_CLK_25_PG8 30
#define R9A06G032_CLK_ADC 31
#define R9A06G032_CLK_ECAT100 32
#define R9A06G032_CLK_HSR100 33
#define R9A06G032_CLK_I2C0 34
#define R9A06G032_CLK_I2C1 35
#define R9A06G032_CLK_MII_REF 36
#define R9A06G032_CLK_NAND 37
#define R9A06G032_CLK_NOUSBP2_PG6 38
#define R9A06G032_CLK_P1_PG2 39
#define R9A06G032_CLK_P1_PG3 40
#define R9A06G032_CLK_P1_PG4 41
#define R9A06G032_CLK_P4_PG3 42
#define R9A06G032_CLK_P4_PG4 43
#define R9A06G032_CLK_P6_PG1 44
#define R9A06G032_CLK_P6_PG2 45
#define R9A06G032_CLK_P6_PG3 46
#define R9A06G032_CLK_P6_PG4 47
#define R9A06G032_CLK_PCI_USB 48
#define R9A06G032_CLK_QSPI0 49
#define R9A06G032_CLK_QSPI1 50
#define R9A06G032_CLK_RGMII_REF 51
#define R9A06G032_CLK_RMII_REF 52
#define R9A06G032_CLK_SDIO0 53
#define R9A06G032_CLK_SDIO1 54
#define R9A06G032_CLK_SERCOS100 55
#define R9A06G032_CLK_SLCD 56
#define R9A06G032_CLK_SPI0 57
#define R9A06G032_CLK_SPI1 58
#define R9A06G032_CLK_SPI2 59
#define R9A06G032_CLK_SPI3 60
#define R9A06G032_CLK_SPI4 61
#define R9A06G032_CLK_SPI5 62
#define R9A06G032_CLK_SWITCH 63
#define R9A06G032_HCLK_ECAT125 65
#define R9A06G032_HCLK_PINCONFIG 66
#define R9A06G032_HCLK_SERCOS 67
#define R9A06G032_HCLK_SGPIO2 68
#define R9A06G032_HCLK_SGPIO3 69
#define R9A06G032_HCLK_SGPIO4 70
#define R9A06G032_HCLK_TIMER0 71
#define R9A06G032_HCLK_TIMER1 72
#define R9A06G032_HCLK_USBF 73
#define R9A06G032_HCLK_USBH 74
#define R9A06G032_HCLK_USBPM 75
#define R9A06G032_CLK_48_PG_F 76
#define R9A06G032_CLK_48_PG4 77
#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */
#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */
#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */
#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */
#define R9A06G032_HCLK_CAN0 85
#define R9A06G032_HCLK_CAN1 86
#define R9A06G032_HCLK_DELTASIGMA 87
#define R9A06G032_HCLK_PWMPTO 88
#define R9A06G032_HCLK_RSV 89
#define R9A06G032_HCLK_SGPIO0 90
#define R9A06G032_HCLK_SGPIO1 91
#define R9A06G032_RTOS_MDC 92
#define R9A06G032_CLK_CM3 93
#define R9A06G032_CLK_DDRC 94
#define R9A06G032_CLK_ECAT25 95
#define R9A06G032_CLK_HSR50 96
#define R9A06G032_CLK_HW_RTOS 97
#define R9A06G032_CLK_SERCOS50 98
#define R9A06G032_HCLK_ADC 99
#define R9A06G032_HCLK_CM3 100
#define R9A06G032_HCLK_CRYPTO_EIP150 101
#define R9A06G032_HCLK_CRYPTO_EIP93 102
#define R9A06G032_HCLK_DDRC 103
#define R9A06G032_HCLK_DMA0 104
#define R9A06G032_HCLK_DMA1 105
#define R9A06G032_HCLK_GMAC0 106
#define R9A06G032_HCLK_GMAC1 107
#define R9A06G032_HCLK_GPIO0 108
#define R9A06G032_HCLK_GPIO1 109
#define R9A06G032_HCLK_GPIO2 110
#define R9A06G032_HCLK_HSR 111
#define R9A06G032_HCLK_I2C0 112
#define R9A06G032_HCLK_I2C1 113
#define R9A06G032_HCLK_LCD 114
#define R9A06G032_HCLK_MSEBI_M 115
#define R9A06G032_HCLK_MSEBI_S 116
#define R9A06G032_HCLK_NAND 117
#define R9A06G032_HCLK_PG_I 118
#define R9A06G032_HCLK_PG19 119
#define R9A06G032_HCLK_PG20 120
#define R9A06G032_HCLK_PG3 121
#define R9A06G032_HCLK_PG4 122
#define R9A06G032_HCLK_QSPI0 123
#define R9A06G032_HCLK_QSPI1 124
#define R9A06G032_HCLK_ROM 125
#define R9A06G032_HCLK_RTC 126
#define R9A06G032_HCLK_SDIO0 127
#define R9A06G032_HCLK_SDIO1 128
#define R9A06G032_HCLK_SEMAP 129
#define R9A06G032_HCLK_SPI0 130
#define R9A06G032_HCLK_SPI1 131
#define R9A06G032_HCLK_SPI2 132
#define R9A06G032_HCLK_SPI3 133
#define R9A06G032_HCLK_SPI4 134
#define R9A06G032_HCLK_SPI5 135
#define R9A06G032_HCLK_SWITCH 136
#define R9A06G032_HCLK_SWITCH_RG 137
#define R9A06G032_HCLK_UART0 138
#define R9A06G032_HCLK_UART1 139
#define R9A06G032_HCLK_UART2 140
#define R9A06G032_HCLK_UART3 141
#define R9A06G032_HCLK_UART4 142
#define R9A06G032_HCLK_UART5 143
#define R9A06G032_HCLK_UART6 144
#define R9A06G032_HCLK_UART7 145
#define R9A06G032_CLK_UART0 146
#define R9A06G032_CLK_UART1 147
#define R9A06G032_CLK_UART2 148
#define R9A06G032_CLK_UART3 149
#define R9A06G032_CLK_UART4 150
#define R9A06G032_CLK_UART5 151
#define R9A06G032_CLK_UART6 152
#define R9A06G032_CLK_UART7 153
#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */
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