Commit ac7da1b7 authored by Stephen Boyd's avatar Stephen Boyd

Merge branches 'clk-actions-s700', 'clk-exynos-unused', 'clk-qcom-dispcc-845',...

Merge branches 'clk-actions-s700', 'clk-exynos-unused', 'clk-qcom-dispcc-845', 'clk-scmi-round' and 'clk-cs2000-spdx' into clk-next

* clk-actions-s700:
  :  - Actions Semi Owl series S700 SoC clk driver
  clk: actions: Add S700 SoC clock support
  dt-bindings: clock: Add S700 support for Actions Semi Soc's
  clk: actions: Add missing REGMAP_MMIO dependency

* clk-exynos-unused:
  :  - Remove an unused variable from Exynos4412 ISP driver
  clk: samsung: Remove unused mout_user_aclk400_mcuisp_p4x12 variable

* clk-qcom-dispcc-845:
  :  - Qualcomm SDM845 display clock controller
  clk: qcom: Add display clock controller driver for SDM845
  dt-bindings: clock: Introduce QCOM Display clock bindings
  clk: qcom: Move frequency table macro to common file

* clk-scmi-round:
  :  - Fix a thinko bug in SCMI clk division logic
  clk: scmi: Fix the rounding of clock rate

* clk-cs2000-spdx:
  clk: cs2000-cp: convert to SPDX identifiers
* Actions S900 Clock Management Unit (CMU)
* Actions Semi Owl Clock Management Unit (CMU)
The Actions S900 clock management unit generates and supplies clock to various
controllers within the SoC. The clock binding described here is applicable to
S900 SoC.
The Actions Semi Owl Clock Management Unit generates and supplies clock
to various controllers within the SoC. The clock binding described here is
applicable to S900 and S700 SoC's.
Required Properties:
- compatible: should be "actions,s900-cmu"
- compatible: should be one of the following,
"actions,s900-cmu"
"actions,s700-cmu"
- reg: physical base address of the controller and length of memory mapped
region.
- clocks: Reference to the parent clocks ("hosc", "losc")
......@@ -15,16 +17,16 @@ Required Properties:
Each clock is assigned an identifier, and client nodes can use this identifier
to specify the clock which they consume.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/actions,s900-cmu.h header and can be used in device
tree sources.
All available clocks are defined as preprocessor macros in corresponding
dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h header and can be
used in device tree sources.
External clocks:
The hosc clock used as input for the plls is generated outside the SoC. It is
expected that it is defined using standard clock bindings as "hosc".
Actions S900 CMU also requires one more clock:
Actions Semi S900 CMU also requires one more clock:
- "losc" - internal low frequency oscillator
Example: Clock Management Unit node:
......
Qualcomm Technologies, Inc. Display Clock Controller Binding
------------------------------------------------------------
Required properties :
- compatible : shall contain "qcom,sdm845-dispcc"
- reg : shall contain base register location and length.
- #clock-cells : from common clock binding, shall contain 1.
- #reset-cells : from common reset binding, shall contain 1.
- #power-domain-cells : from generic power domain binding, shall contain 1.
Example:
dispcc: clock-controller@af00000 {
compatible = "qcom,sdm845-dispcc";
reg = <0xaf00000 0x100000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
config CLK_ACTIONS
bool "Clock driver for Actions Semi SoCs"
depends on ARCH_ACTIONS || COMPILE_TEST
select REGMAP_MMIO
default ARCH_ACTIONS
if CLK_ACTIONS
# SoC Drivers
config CLK_OWL_S700
bool "Support for the Actions Semi OWL S700 clocks"
depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
default ARM64 && ARCH_ACTIONS
config CLK_OWL_S900
bool "Support for the Actions Semi OWL S900 clocks"
depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
default ARM64 && ARCH_ACTIONS
endif
......@@ -9,4 +9,5 @@ clk-owl-y += owl-composite.o
clk-owl-y += owl-pll.o
# SoC support
obj-$(CONFIG_CLK_OWL_S700) += owl-s700.o
obj-$(CONFIG_CLK_OWL_S900) += owl-s900.o
This diff is collapsed.
// SPDX-License-Identifier: GPL-2.0
/*
* CS2000 -- CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
*
* Copyright (C) 2015 Renesas Electronics Corporation
* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/clk-provider.h>
#include <linux/delay.h>
......
......@@ -38,7 +38,6 @@ static unsigned long scmi_clk_recalc_rate(struct clk_hw *hw,
static long scmi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
int step;
u64 fmin, fmax, ftmp;
struct scmi_clk *clk = to_scmi_clk(hw);
......@@ -60,9 +59,9 @@ static long scmi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
ftmp = rate - fmin;
ftmp += clk->info->range.step_size - 1; /* to round up */
step = do_div(ftmp, clk->info->range.step_size);
do_div(ftmp, clk->info->range.step_size);
return step * clk->info->range.step_size + fmin;
return ftmp * clk->info->range.step_size + fmin;
}
static int scmi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
......
......@@ -254,6 +254,16 @@ config SDM_VIDEOCC_845
Say Y if you want to support video devices and functionality such as
video encode and decode.
config SDM_DISPCC_845
tristate "SDM845 Display Clock Controller"
select SDM_GCC_845
depends on COMMON_CLK_QCOM
help
Support for the display clock controller on Qualcomm Technologies, Inc
SDM845 devices.
Say Y if you want to support display devices and functionality such as
splash screen.
config SPMI_PMIC_CLKDIV
tristate "SPMI PMIC clkdiv Support"
depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
......
......@@ -39,6 +39,7 @@ obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
......@@ -7,6 +7,8 @@
#include <linux/clk-provider.h>
#include "clk-regmap.h"
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
struct freq_tbl {
unsigned long freq;
u8 src;
......
This diff is collapsed.
......@@ -106,8 +106,6 @@ static const char * const gcc_xo_pcie_sleep[] = {
"sleep_clk_src",
};
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
static struct clk_pll gpll0 = {
.l_reg = 0x0004,
.m_reg = 0x0008,
......
......@@ -179,8 +179,6 @@ static const char * const gcc_xo_ddr_500_200[] = {
"ddrpllapss",
};
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = {
F(48000000, P_XO, 1, 0, 0),
F(200000000, P_FEPLL200, 1, 0, 0),
......
......@@ -32,8 +32,6 @@
#include "clk-regmap-mux.h"
#include "reset.h"
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
enum {
P_XO,
P_GPLL0,
......
......@@ -264,8 +264,6 @@ static const char * const gcc_xo_gpll1_emclk_sleep[] = {
"sleep_clk",
};
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
static struct clk_pll gpll0 = {
.l_reg = 0x21004,
.m_reg = 0x21008,
......
......@@ -62,8 +62,6 @@ static const char * const gcc_xo_gpll0_gpll4[] = {
"gpll4_vote",
};
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
static struct clk_pll gpll0 = {
.l_reg = 0x0004,
.m_reg = 0x0008,
......
......@@ -57,8 +57,6 @@ static const char * const gcc_xo_gpll0_gpll4[] = {
"gpll4",
};
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
static struct clk_fixed_factor xo = {
.mult = 1,
.div = 1,
......
......@@ -32,8 +32,6 @@
#include "reset.h"
#include "gdsc.h"
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
enum {
P_XO,
P_GPLL0,
......
......@@ -25,8 +25,6 @@
#include "reset.h"
#include "gdsc.h"
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
enum {
P_AUD_REF_CLK,
P_CORE_BI_PLL_TEST_SE,
......
......@@ -25,8 +25,6 @@
#include "gdsc.h"
#include "reset.h"
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
enum {
P_BI_TCXO,
P_AUD_REF_CLK,
......
......@@ -219,8 +219,6 @@ static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
"sleep_clk_src",
};
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
static struct clk_pll mmpll0 = {
.l_reg = 0x0004,
.m_reg = 0x0008,
......
......@@ -184,8 +184,6 @@ static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
"dsi1pllbyte",
};
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
static struct clk_pll mmpll0 = {
.l_reg = 0x0004,
.m_reg = 0x0008,
......
......@@ -34,8 +34,6 @@
#include "reset.h"
#include "gdsc.h"
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
enum {
P_XO,
P_MMPLL0,
......
......@@ -18,8 +18,6 @@
#include "clk-pll.h"
#include "gdsc.h"
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
enum {
P_BI_TCXO,
P_CORE_BI_PLL_TEST_SE,
......
......@@ -37,8 +37,6 @@ static const unsigned long exynos4x12_clk_isp_save[] __initconst = {
E4X12_GATE_ISP1,
};
PNAME(mout_user_aclk400_mcuisp_p4x12) = { "fin_pll", "div_aclk400_mcuisp", };
static struct samsung_div_clock exynos4x12_isp_div_clks[] = {
DIV(CLK_ISP_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
DIV(CLK_ISP_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
......
/* SPDX-License-Identifier: GPL-2.0
*
* Device Tree binding constants for Actions Semi S700 Clock Management Unit
*
* Copyright (c) 2014 Actions Semi Inc.
* Author: David Liu <liuwei@actions-semi.com>
*
* Author: Pathiban Nallathambi <pn@denx.de>
* Author: Saravanan Sekar <sravanhome@gmail.com>
*/
#ifndef __DT_BINDINGS_CLOCK_S700_H
#define __DT_BINDINGS_CLOCK_S700_H
#define CLK_NONE 0
/* pll clocks */
#define CLK_CORE_PLL 1
#define CLK_DEV_PLL 2
#define CLK_DDR_PLL 3
#define CLK_NAND_PLL 4
#define CLK_DISPLAY_PLL 5
#define CLK_TVOUT_PLL 6
#define CLK_CVBS_PLL 7
#define CLK_AUDIO_PLL 8
#define CLK_ETHERNET_PLL 9
/* system clock */
#define CLK_CPU 10
#define CLK_DEV 11
#define CLK_AHB 12
#define CLK_APB 13
#define CLK_DMAC 14
#define CLK_NOC0_CLK_MUX 15
#define CLK_NOC1_CLK_MUX 16
#define CLK_HP_CLK_MUX 17
#define CLK_HP_CLK_DIV 18
#define CLK_NOC1_CLK_DIV 19
#define CLK_NOC0 20
#define CLK_NOC1 21
#define CLK_SENOR_SRC 22
/* peripheral device clock */
#define CLK_GPIO 23
#define CLK_TIMER 24
#define CLK_DSI 25
#define CLK_CSI 26
#define CLK_SI 27
#define CLK_DE 28
#define CLK_HDE 29
#define CLK_VDE 30
#define CLK_VCE 31
#define CLK_NAND 32
#define CLK_SD0 33
#define CLK_SD1 34
#define CLK_SD2 35
#define CLK_UART0 36
#define CLK_UART1 37
#define CLK_UART2 38
#define CLK_UART3 39
#define CLK_UART4 40
#define CLK_UART5 41
#define CLK_UART6 42
#define CLK_PWM0 43
#define CLK_PWM1 44
#define CLK_PWM2 45
#define CLK_PWM3 46
#define CLK_PWM4 47
#define CLK_PWM5 48
#define CLK_GPU3D 49
#define CLK_I2C0 50
#define CLK_I2C1 51
#define CLK_I2C2 52
#define CLK_I2C3 53
#define CLK_SPI0 54
#define CLK_SPI1 55
#define CLK_SPI2 56
#define CLK_SPI3 57
#define CLK_USB3_480MPLL0 58
#define CLK_USB3_480MPHY0 59
#define CLK_USB3_5GPHY 60
#define CLK_USB3_CCE 61
#define CLK_USB3_MAC 62
#define CLK_LCD 63
#define CLK_HDMI_AUDIO 64
#define CLK_I2SRX 65
#define CLK_I2STX 66
#define CLK_SENSOR0 67
#define CLK_SENSOR1 68
#define CLK_HDMI_DEV 69
#define CLK_ETHERNET 70
#define CLK_RMII_REF 71
#define CLK_USB2H0_PLLEN 72
#define CLK_USB2H0_PHY 73
#define CLK_USB2H0_CCE 74
#define CLK_USB2H1_PLLEN 75
#define CLK_USB2H1_PHY 76
#define CLK_USB2H1_CCE 77
#define CLK_TVOUT 78
#define CLK_THERMAL_SENSOR 79
#define CLK_IRC_SWITCH 80
#define CLK_PCM1 81
#define CLK_NR_CLKS (CLK_PCM1 + 1)
#endif /* __DT_BINDINGS_CLOCK_S700_H */
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
/* DISP_CC clock registers */
#define DISP_CC_MDSS_AHB_CLK 0
#define DISP_CC_MDSS_AXI_CLK 1
#define DISP_CC_MDSS_BYTE0_CLK 2
#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
#define DISP_CC_MDSS_BYTE0_INTF_CLK 4
#define DISP_CC_MDSS_BYTE1_CLK 5
#define DISP_CC_MDSS_BYTE1_CLK_SRC 6
#define DISP_CC_MDSS_BYTE1_INTF_CLK 7
#define DISP_CC_MDSS_ESC0_CLK 8
#define DISP_CC_MDSS_ESC0_CLK_SRC 9
#define DISP_CC_MDSS_ESC1_CLK 10
#define DISP_CC_MDSS_ESC1_CLK_SRC 11
#define DISP_CC_MDSS_MDP_CLK 12
#define DISP_CC_MDSS_MDP_CLK_SRC 13
#define DISP_CC_MDSS_MDP_LUT_CLK 14
#define DISP_CC_MDSS_PCLK0_CLK 15
#define DISP_CC_MDSS_PCLK0_CLK_SRC 16
#define DISP_CC_MDSS_PCLK1_CLK 17
#define DISP_CC_MDSS_PCLK1_CLK_SRC 18
#define DISP_CC_MDSS_ROT_CLK 19
#define DISP_CC_MDSS_ROT_CLK_SRC 20
#define DISP_CC_MDSS_RSCC_AHB_CLK 21
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22
#define DISP_CC_MDSS_VSYNC_CLK 23
#define DISP_CC_MDSS_VSYNC_CLK_SRC 24
#define DISP_CC_PLL0 25
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27
/* DISP_CC Reset */
#define DISP_CC_MDSS_RSCC_BCR 0
/* DISP_CC GDSCR */
#define MDSS_GDSC 0
#endif
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