Commit de64f5c8 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-4.9' of...

Merge tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Pull Allwinner clock driver changes from Maxime Ripard:

Four more SoCs converted to the new clock framework (A31, A31s, A23 and
A33).

* tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  clk: sunxi-ng: Add hardware dependency
  clk: sunxi-ng: Add A23 CCU
  clk: sunxi-ng: Add A33 CCU support
  clk: sunxi-ng: Add N-class clocks support
  clk: sunxi-ng: mux: Add mux table macro
  clk: sunxi-ng: div: Allow to set a maximum
  clk: sunxi-ng: div: Add kerneldoc for the _ccu_div structure
  clk: sunxi-ng: div: Add mux table macros
  clk: sunxi-ng: Add A31/A31s clocks
  clk: sunxi-ng: mux: Add clk notifier functions
  clk: sunxi-ng: mux: support fixed pre-dividers on multiple parents
  clk: sunxi-ng: mux: Add support for mux tables
  clk: sunxi-ng: mux: Rename mux macro to be consistent
  clk: sunxi-ng: nkm: Add mux to support multiple parents
  clk: sunxi-ng: mux: Increase fixed pre-divider div size
parents 3db385ea d63a5e7c
......@@ -2,7 +2,10 @@ Allwinner Clock Control Unit Binding
------------------------------------
Required properties :
- compatible: must contain one of the following compatible:
- compatible: must contain one of the following compatibles:
- "allwinner,sun6i-a31-ccu"
- "allwinner,sun8i-a23-ccu"
- "allwinner,sun8i-a33-ccu"
- "allwinner,sun8i-h3-ccu"
- reg: Must contain the registers base address and length
......
config SUNXI_CCU
bool "Clock support for Allwinner SoCs"
depends on ARCH_SUNXI || COMPILE_TEST
default ARCH_SUNXI
if SUNXI_CCU
......@@ -19,6 +20,10 @@ config SUNXI_CCU_GATE
config SUNXI_CCU_MUX
bool
config SUNXI_CCU_MULT
bool
select SUNXI_CCU_MUX
config SUNXI_CCU_PHASE
bool
......@@ -51,6 +56,40 @@ config SUNXI_CCU_MP
# SoC Drivers
config SUN6I_A31_CCU
bool "Support for the Allwinner A31/A31s CCU"
select SUNXI_CCU_DIV
select SUNXI_CCU_NK
select SUNXI_CCU_NKM
select SUNXI_CCU_NM
select SUNXI_CCU_MP
select SUNXI_CCU_PHASE
default MACH_SUN6I
config SUN8I_A23_CCU
bool "Support for the Allwinner A23 CCU"
select SUNXI_CCU_DIV
select SUNXI_CCU_MULT
select SUNXI_CCU_NK
select SUNXI_CCU_NKM
select SUNXI_CCU_NKMP
select SUNXI_CCU_NM
select SUNXI_CCU_MP
select SUNXI_CCU_PHASE
default MACH_SUN8I
config SUN8I_A33_CCU
bool "Support for the Allwinner A33 CCU"
select SUNXI_CCU_DIV
select SUNXI_CCU_MULT
select SUNXI_CCU_NK
select SUNXI_CCU_NKM
select SUNXI_CCU_NKMP
select SUNXI_CCU_NM
select SUNXI_CCU_MP
select SUNXI_CCU_PHASE
default MACH_SUN8I
config SUN8I_H3_CCU
bool "Support for the Allwinner H3 CCU"
select SUNXI_CCU_DIV
......
......@@ -7,6 +7,7 @@ obj-$(CONFIG_SUNXI_CCU_DIV) += ccu_div.o
obj-$(CONFIG_SUNXI_CCU_FRAC) += ccu_frac.o
obj-$(CONFIG_SUNXI_CCU_GATE) += ccu_gate.o
obj-$(CONFIG_SUNXI_CCU_MUX) += ccu_mux.o
obj-$(CONFIG_SUNXI_CCU_MULT) += ccu_mult.o
obj-$(CONFIG_SUNXI_CCU_PHASE) += ccu_phase.o
# Multi-factor clocks
......@@ -17,4 +18,7 @@ obj-$(CONFIG_SUNXI_CCU_NM) += ccu_nm.o
obj-$(CONFIG_SUNXI_CCU_MP) += ccu_mp.o
# SoC support
obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
This diff is collapsed.
/*
* Copyright 2016 Chen-Yu Tsai
*
* Chen-Yu Tsai <wens@csie.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _CCU_SUN6I_A31_H_
#define _CCU_SUN6I_A31_H_
#include <dt-bindings/clock/sun6i-a31-ccu.h>
#include <dt-bindings/reset/sun6i-a31-ccu.h>
#define CLK_PLL_CPU 0
#define CLK_PLL_AUDIO_BASE 1
#define CLK_PLL_AUDIO 2
#define CLK_PLL_AUDIO_2X 3
#define CLK_PLL_AUDIO_4X 4
#define CLK_PLL_AUDIO_8X 5
#define CLK_PLL_VIDEO0 6
#define CLK_PLL_VIDEO0_2X 7
#define CLK_PLL_VE 8
#define CLK_PLL_DDR 9
/* The PLL_PERIPH clock is exported */
#define CLK_PLL_PERIPH_2X 11
#define CLK_PLL_VIDEO1 12
#define CLK_PLL_VIDEO1_2X 13
#define CLK_PLL_GPU 14
#define CLK_PLL_MIPI 15
#define CLK_PLL9 16
#define CLK_PLL10 17
/* The CPUX clock is exported */
#define CLK_AXI 19
#define CLK_AHB1 20
#define CLK_APB1 21
#define CLK_APB2 22
/* All the bus gates are exported */
/* The first bunch of module clocks are exported */
/* EMAC clock is not implemented */
#define CLK_MDFS 107
#define CLK_SDRAM0 108
#define CLK_SDRAM1 109
/* All the DRAM gates are exported */
/* Some more module clocks are exported */
#define CLK_MBUS0 141
#define CLK_MBUS1 142
/* Some more module clocks and external clock outputs are exported */
#define CLK_NUMBER (CLK_OUT_C + 1)
#endif /* _CCU_SUN6I_A31_H_ */
/*
* Copyright 2016 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _CCU_SUN8I_A23_A33_H_
#define _CCU_SUN8I_A23_A33_H_
#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
#define CLK_PLL_CPUX 0
#define CLK_PLL_AUDIO_BASE 1
#define CLK_PLL_AUDIO 2
#define CLK_PLL_AUDIO_2X 3
#define CLK_PLL_AUDIO_4X 4
#define CLK_PLL_AUDIO_8X 5
#define CLK_PLL_VIDEO 6
#define CLK_PLL_VIDEO_2X 7
#define CLK_PLL_VE 8
#define CLK_PLL_DDR0 9
#define CLK_PLL_PERIPH 10
#define CLK_PLL_PERIPH_2X 11
#define CLK_PLL_GPU 12
#define CLK_PLL_MIPI 13
#define CLK_PLL_HSIC 14
#define CLK_PLL_DE 15
#define CLK_PLL_DDR1 16
#define CLK_PLL_DDR 17
/* The CPUX clock is exported */
#define CLK_AXI 19
#define CLK_AHB1 20
#define CLK_APB1 21
#define CLK_APB2 22
/* All the bus gates are exported */
/* The first part of the mod clocks is exported */
#define CLK_DRAM 79
/* Some more module clocks are exported */
#define CLK_MBUS 95
/* And the last module clocks are exported */
#define CLK_NUMBER (CLK_ATS + 1)
#endif /* _CCU_SUN8I_A23_A33_H_ */
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......@@ -184,15 +184,15 @@ static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
0);
static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
{ .index = 1, .div = 2 },
};
static struct ccu_mux ahb2_clk = {
.mux = {
.shift = 0,
.width = 1,
.fixed_prediv = {
.index = 1,
.div = 2,
},
.fixed_predivs = ahb2_fixed_predivs,
.n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),
},
.common = {
......
......@@ -19,10 +19,29 @@
#include "ccu_common.h"
#include "ccu_mux.h"
/**
* struct _ccu_div - Internal divider description
* @shift: Bit offset of the divider in its register
* @width: Width of the divider field in its register
* @max: Maximum value allowed for that divider. This is the
* arithmetic value, not the maximum value to be set in the
* register.
* @flags: clk_divider flags to apply on this divider
* @table: Divider table pointer (if applicable)
*
* That structure represents a single divider, and is meant to be
* embedded in other structures representing the various clock
* classes.
*
* It is basically a wrapper around the clk_divider functions
* arguments.
*/
struct _ccu_div {
u8 shift;
u8 width;
u32 max;
u32 flags;
struct clk_div_table *table;
......@@ -36,14 +55,25 @@ struct _ccu_div {
.table = _table, \
}
#define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \
_SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, NULL, _flags)
#define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \
_SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, 0)
#define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \
{ \
.shift = _shift, \
.width = _width, \
.flags = _flags, \
.max = _max, \
}
#define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \
_SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags)
#define _SUNXI_CCU_DIV_MAX(_shift, _width, _max) \
_SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, 0)
#define _SUNXI_CCU_DIV(_shift, _width) \
_SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, NULL, 0)
_SUNXI_CCU_DIV_FLAGS(_shift, _width, 0)
struct ccu_div {
u32 enable;
......@@ -77,13 +107,16 @@ struct ccu_div {
_shift, _width, _table, 0, \
_flags)
#define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
_mshift, _mwidth, _muxshift, _muxwidth, \
_gate, _flags) \
#define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
_parents, _table, \
_reg, \
_mshift, _mwidth, \
_muxshift, _muxwidth, \
_gate, _flags) \
struct ccu_div _struct = { \
.enable = _gate, \
.div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
.mux = SUNXI_CLK_MUX(_muxshift, _muxwidth), \
.mux = _SUNXI_CCU_MUX_TABLE(_muxshift, _muxwidth, _table), \
.common = { \
.reg = _reg, \
.hw.init = CLK_HW_INIT_PARENTS(_name, \
......@@ -93,12 +126,23 @@ struct ccu_div {
}, \
}
#define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
_mshift, _mwidth, _muxshift, _muxwidth, \
_gate, _flags) \
SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
_parents, NULL, \
_reg, _mshift, _mwidth, \
_muxshift, _muxwidth, \
_gate, _flags)
#define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \
_mshift, _mwidth, _muxshift, _muxwidth, \
_flags) \
SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
_mshift, _mwidth, _muxshift, _muxwidth, \
0, _flags)
SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
_parents, NULL, \
_reg, _mshift, _mwidth, \
_muxshift, _muxwidth, \
0, _flags)
#define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
......
......@@ -21,9 +21,9 @@ static void ccu_mp_find_best(unsigned long parent, unsigned long rate,
unsigned int best_m = 0, best_p = 0;
unsigned int _m, _p;
for (_p = 0; _p <= max_p; _p++) {
for (_p = 1; _p <= max_p; _p <<= 1) {
for (_m = 1; _m <= max_m; _m++) {
unsigned long tmp_rate = (parent >> _p) / _m;
unsigned long tmp_rate = parent / _p / _m;
if (tmp_rate > rate)
continue;
......@@ -46,13 +46,15 @@ static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
void *data)
{
struct ccu_mp *cmp = data;
unsigned int max_m, max_p;
unsigned int m, p;
ccu_mp_find_best(parent_rate, rate,
1 << cmp->m.width, (1 << cmp->p.width) - 1,
&m, &p);
max_m = cmp->m.max ?: 1 << cmp->m.width;
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
return (parent_rate >> p) / m;
ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p);
return parent_rate / p / m;
}
static void ccu_mp_disable(struct clk_hw *hw)
......@@ -108,13 +110,14 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
{
struct ccu_mp *cmp = hw_to_ccu_mp(hw);
unsigned long flags;
unsigned int max_m, max_p;
unsigned int m, p;
u32 reg;
ccu_mp_find_best(parent_rate, rate,
1 << cmp->m.width, (1 << cmp->p.width) - 1,
&m, &p);
max_m = cmp->m.max ?: 1 << cmp->m.width;
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p);
spin_lock_irqsave(cmp->common.lock, flags);
......@@ -122,7 +125,7 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);
reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);
writel(reg | (p << cmp->p.shift) | ((m - 1) << cmp->m.shift),
writel(reg | (ilog2(p) << cmp->p.shift) | ((m - 1) << cmp->m.shift),
cmp->common.base + cmp->common.reg);
spin_unlock_irqrestore(cmp->common.lock, flags);
......
......@@ -44,7 +44,7 @@ struct ccu_mp {
.enable = _gate, \
.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
.p = _SUNXI_CCU_DIV(_pshift, _pwidth), \
.mux = SUNXI_CLK_MUX(_muxshift, _muxwidth), \
.mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
.common = { \
.reg = _reg, \
.hw.init = CLK_HW_INIT_PARENTS(_name, \
......
/*
* Copyright (C) 2016 Maxime Ripard
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#include <linux/clk-provider.h>
#include "ccu_gate.h"
#include "ccu_mult.h"
static void ccu_mult_find_best(unsigned long parent, unsigned long rate,
unsigned int max_n, unsigned int *n)
{
*n = rate / parent;
}
static unsigned long ccu_mult_round_rate(struct ccu_mux_internal *mux,
unsigned long parent_rate,
unsigned long rate,
void *data)
{
struct ccu_mult *cm = data;
unsigned int n;
ccu_mult_find_best(parent_rate, rate, 1 << cm->mult.width, &n);
return parent_rate * n;
}
static void ccu_mult_disable(struct clk_hw *hw)
{
struct ccu_mult *cm = hw_to_ccu_mult(hw);
return ccu_gate_helper_disable(&cm->common, cm->enable);
}
static int ccu_mult_enable(struct clk_hw *hw)
{
struct ccu_mult *cm = hw_to_ccu_mult(hw);
return ccu_gate_helper_enable(&cm->common, cm->enable);
}
static int ccu_mult_is_enabled(struct clk_hw *hw)
{
struct ccu_mult *cm = hw_to_ccu_mult(hw);
return ccu_gate_helper_is_enabled(&cm->common, cm->enable);
}
static unsigned long ccu_mult_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_mult *cm = hw_to_ccu_mult(hw);
unsigned long val;
u32 reg;
reg = readl(cm->common.base + cm->common.reg);
val = reg >> cm->mult.shift;
val &= (1 << cm->mult.width) - 1;
ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
&parent_rate);
return parent_rate * (val + 1);
}
static int ccu_mult_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct ccu_mult *cm = hw_to_ccu_mult(hw);
return ccu_mux_helper_determine_rate(&cm->common, &cm->mux,
req, ccu_mult_round_rate, cm);
}
static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct ccu_mult *cm = hw_to_ccu_mult(hw);
unsigned long flags;
unsigned int n;
u32 reg;
ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
&parent_rate);
ccu_mult_find_best(parent_rate, rate, 1 << cm->mult.width, &n);
spin_lock_irqsave(cm->common.lock, flags);
reg = readl(cm->common.base + cm->common.reg);
reg &= ~GENMASK(cm->mult.width + cm->mult.shift - 1, cm->mult.shift);
writel(reg | ((n - 1) << cm->mult.shift),
cm->common.base + cm->common.reg);
spin_unlock_irqrestore(cm->common.lock, flags);
return 0;
}
static u8 ccu_mult_get_parent(struct clk_hw *hw)
{
struct ccu_mult *cm = hw_to_ccu_mult(hw);
return ccu_mux_helper_get_parent(&cm->common, &cm->mux);
}
static int ccu_mult_set_parent(struct clk_hw *hw, u8 index)
{
struct ccu_mult *cm = hw_to_ccu_mult(hw);
return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index);
}
const struct clk_ops ccu_mult_ops = {
.disable = ccu_mult_disable,
.enable = ccu_mult_enable,
.is_enabled = ccu_mult_is_enabled,
.get_parent = ccu_mult_get_parent,
.set_parent = ccu_mult_set_parent,
.determine_rate = ccu_mult_determine_rate,
.recalc_rate = ccu_mult_recalc_rate,
.set_rate = ccu_mult_set_rate,
};
#ifndef _CCU_MULT_H_
#define _CCU_MULT_H_
#include "ccu_common.h"
#include "ccu_mux.h"
struct _ccu_mult {
u8 shift;
u8 width;
......@@ -12,4 +15,36 @@ struct _ccu_mult {
.width = _width, \
}
struct ccu_mult {
u32 enable;
struct _ccu_mult mult;
struct ccu_mux_internal mux;
struct ccu_common common;
};
#define SUNXI_CCU_N_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \
_mshift, _mwidth, _gate, _lock, \
_flags) \
struct ccu_mult _struct = { \
.enable = _gate, \
.mult = _SUNXI_CCU_MULT(_mshift, _mwidth), \
.common = { \
.reg = _reg, \
.hw.init = CLK_HW_INIT(_name, \
_parent, \
&ccu_mult_ops, \
_flags), \
}, \
}
static inline struct ccu_mult *hw_to_ccu_mult(struct clk_hw *hw)
{
struct ccu_common *common = hw_to_ccu_common(hw);
return container_of(common, struct ccu_mult, common);
}
extern const struct clk_ops ccu_mult_ops;
#endif /* _CCU_MULT_H_ */
......@@ -8,7 +8,9 @@
* the License, or (at your option) any later version.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include "ccu_gate.h"
#include "ccu_mux.h"
......@@ -18,8 +20,9 @@ void ccu_mux_helper_adjust_parent_for_prediv(struct ccu_common *common,
int parent_index,
unsigned long *parent_rate)
{
u8 prediv = 1;
u16 prediv = 1;