Commit fb960bd2 authored by Feifei Xu's avatar Feifei Xu Committed by Alex Deucher
Browse files

drm/amd/include:cleanup vega10 header files.



Remove asic_reg/vega10 folder.

Signed-off-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8af7454e
......@@ -35,7 +35,7 @@
#include "soc15d.h"
#include "soc15_common.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "raven1/VCN/vcn_1_0_offset.h"
/* 1 second timeout */
......
......@@ -28,10 +28,10 @@
#include "soc15.h"
#include "soc15d.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "gc/gc_9_0_offset.h"
#include "gc/gc_9_0_sh_mask.h"
#include "vega10/vega10_enum.h"
#include "vega10_enum.h"
#include "hdp/hdp_4_0_offset.h"
#include "soc15_common.h"
......
......@@ -23,11 +23,11 @@
#include "amdgpu.h"
#include "gfxhub_v1_0.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "gc/gc_9_0_offset.h"
#include "gc/gc_9_0_sh_mask.h"
#include "gc/gc_9_0_default.h"
#include "vega10/vega10_enum.h"
#include "vega10_enum.h"
#include "soc15_common.h"
......
......@@ -25,13 +25,13 @@
#include "gmc_v9_0.h"
#include "amdgpu_atomfirmware.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "hdp/hdp_4_0_offset.h"
#include "hdp/hdp_4_0_sh_mask.h"
#include "gc/gc_9_0_sh_mask.h"
#include "dce/dce_12_0_offset.h"
#include "dce/dce_12_0_sh_mask.h"
#include "vega10/vega10_enum.h"
#include "vega10_enum.h"
#include "mmhub/mmhub_1_0_offset.h"
#include "athub/athub_1_0_offset.h"
......
......@@ -23,13 +23,13 @@
#include "amdgpu.h"
#include "mmhub_v1_0.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "mmhub/mmhub_1_0_offset.h"
#include "mmhub/mmhub_1_0_sh_mask.h"
#include "mmhub/mmhub_1_0_default.h"
#include "athub/athub_1_0_offset.h"
#include "athub/athub_1_0_sh_mask.h"
#include "vega10/vega10_enum.h"
#include "vega10_enum.h"
#include "soc15_common.h"
......
......@@ -22,7 +22,7 @@
*/
#include "amdgpu.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "nbio/nbio_6_1_offset.h"
#include "nbio/nbio_6_1_sh_mask.h"
#include "gc/gc_9_0_offset.h"
......
......@@ -24,11 +24,11 @@
#include "amdgpu_atombios.h"
#include "nbio_v6_1.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "nbio/nbio_6_1_default.h"
#include "nbio/nbio_6_1_offset.h"
#include "nbio/nbio_6_1_sh_mask.h"
#include "vega10/vega10_enum.h"
#include "vega10_enum.h"
#define smnCPM_CONTROL 0x11180460
#define smnPCIE_CNTL2 0x11180070
......
......@@ -24,11 +24,11 @@
#include "amdgpu_atombios.h"
#include "nbio_v7_0.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "raven1/NBIO/nbio_7_0_default.h"
#include "raven1/NBIO/nbio_7_0_offset.h"
#include "raven1/NBIO/nbio_7_0_sh_mask.h"
#include "vega10/vega10_enum.h"
#include "vega10_enum.h"
#define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c
......
......@@ -30,7 +30,7 @@
#include "soc15_common.h"
#include "psp_v10_0.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "raven1/MP/mp_10_0_offset.h"
#include "raven1/GC/gc_9_1_offset.h"
#include "raven1/SDMA0/sdma0_4_1_offset.h"
......
......@@ -31,7 +31,7 @@
#include "soc15_common.h"
#include "psp_v3_1.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "mp/mp_9_0_offset.h"
#include "mp/mp_9_0_sh_mask.h"
#include "gc/gc_9_0_offset.h"
......
......@@ -27,7 +27,7 @@
#include "amdgpu_ucode.h"
#include "amdgpu_trace.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "sdma0/sdma0_4_0_offset.h"
#include "sdma0/sdma0_4_0_sh_mask.h"
#include "sdma1/sdma1_4_0_offset.h"
......
......@@ -34,7 +34,7 @@
#include "atom.h"
#include "amd_pcie.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "uvd/uvd_7_0_offset.h"
#include "gc/gc_9_0_offset.h"
#include "gc/gc_9_0_sh_mask.h"
......
......@@ -29,7 +29,7 @@
#include "soc15_common.h"
#include "mmsch_v1_0.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "uvd/uvd_7_0_offset.h"
#include "uvd/uvd_7_0_sh_mask.h"
#include "vce/vce_4_0_offset.h"
......
......@@ -32,7 +32,7 @@
#include "soc15_common.h"
#include "mmsch_v1_0.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "vce/vce_4_0_offset.h"
#include "vce/vce_4_0_default.h"
#include "vce/vce_4_0_sh_mask.h"
......
......@@ -28,7 +28,7 @@
#include "soc15d.h"
#include "soc15_common.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "raven1/VCN/vcn_1_0_offset.h"
#include "raven1/VCN/vcn_1_0_sh_mask.h"
#include "hdp/hdp_4_0_offset.h"
......
......@@ -26,7 +26,7 @@
#include "soc15.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "oss/osssys_4_0_offset.h"
#include "oss/osssys_4_0_sh_mask.h"
......
......@@ -61,7 +61,7 @@
#include "raven1/DCN/dcn_1_0_offset.h"
#include "raven1/DCN/dcn_1_0_sh_mask.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "soc15_common.h"
#endif
......
......@@ -33,7 +33,7 @@
#include "dce/dce_12_0_offset.h"
#include "dce/dce_12_0_sh_mask.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "reg_helper.h"
#define CTX \
......
......@@ -56,7 +56,7 @@
#include "dce/dce_12_0_offset.h"
#include "dce/dce_12_0_sh_mask.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "nbio/nbio_6_1_offset.h"
#include "reg_helper.h"
......
......@@ -27,7 +27,7 @@
#include "dce/dce_12_0_offset.h"
#include "dce/dce_12_0_sh_mask.h"
#include "vega10/soc15ip.h"
#include "soc15ip.h"
#include "dc_types.h"
#include "dc_bios_types.h"
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment