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  1. 15 Jun, 2018 2 commits
    • Jose Abreu's avatar
      net: stmmac: Run HWIF Quirks after getting HW caps · 7cfde0af
      Jose Abreu authored
      
      
      Currently we were running HWIF quirks before getting HW capabilities.
      This is not right because some HWIF callbacks depend on HW caps.
      
      Lets save the quirks callback and use it in a later stage.
      
      This fixes Altera socfpga.
      Signed-off-by: default avatarJose Abreu <joabreu@synopsys.com>
      Fixes: 5f0456b4
      
       ("net: stmmac: Implement logic to automatically select HW Interface")
      Reported-by: default avatarDinh Nguyen <dinh.linux@gmail.com>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Joao Pinto <jpinto@synopsys.com>
      Cc: Vitor Soares <soares@synopsys.com>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Cc: Dinh Nguyen <dinh.linux@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      7cfde0af
    • Elad Nachman's avatar
      stmmac: added support for 802.1ad vlan stripping · ab188e8f
      Elad Nachman authored
      
      
      stmmac reception handler calls stmmac_rx_vlan() to strip the vlan before
      calling napi_gro_receive().
      
      The function assumes VLAN tagged frames are always tagged with
      802.1Q protocol, and assigns ETH_P_8021Q to the skb by hard-coding
      the parameter on call to __vlan_hwaccel_put_tag() .
      
      This causes packets not to be passed to the VLAN slave if it was created
      with 802.1AD protocol
      (ip link add link eth0 eth0.100 type vlan proto 802.1ad id 100).
      
      This fix passes the protocol from the VLAN header into
      __vlan_hwaccel_put_tag() instead of using the hard-coded value of
      ETH_P_8021Q.
      
      NETIF_F_HW_VLAN_STAG_RX check was added and the strip action is now
      dependent on the correct combination of features and the detected vlan tag.
      
      NETIF_F_HW_VLAN_STAG_RX feature was added to be in line with the driver
      actual abilities.
      Signed-off-by: default avatarElad Nachman <eladn@gilat.com>
      Reviewed-by: default avatarToshiaki Makita <makita.toshiaki@lab.ntt.co.jp>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      ab188e8f
  2. 04 Jun, 2018 1 commit
    • Jose Abreu's avatar
      net: stmmac: Add Flexible PPS support · 9a8a02c9
      Jose Abreu authored
      
      
      This adds support for Flexible PPS output (which is equivalent
      to per_out output of PTP subsystem).
      
      Tested using an oscilloscope and the following commands:
      
      1) Start PTP4L:
      	# ptp4l -A -4 -H -m -i eth0 &
      2) Set Flexible PPS frequency:
      	# echo <idx> <ts> <tns> <ps> <pns> > /sys/class/ptp/ptpX/period
      
      Where, ts/tns is start time and ps/pns is period time, and ptpX is ptp
      of eth0.
      Signed-off-by: default avatarJose Abreu <joabreu@synopsys.com>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Joao Pinto <jpinto@synopsys.com>
      Cc: Vitor Soares <soares@synopsys.com>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Cc: Richard Cochran <richardcochran@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      9a8a02c9
  3. 29 May, 2018 1 commit
  4. 18 May, 2018 11 commits
  5. 10 May, 2018 1 commit
    • Jose Abreu's avatar
      net: stmmac: Add support for U32 TC filter using Flexible RX Parser · 4dbbe8dd
      Jose Abreu authored
      
      
      This adds support for U32 filter by using an HW only feature called
      Flexible RX Parser. This allow us to match any given packet field with a
      pattern and accept/reject or even route the packet to a specific DMA
      channel.
      
      Right now we only support acception or rejection of frame and we only
      support simple rules. Though, the Parser has the flexibility of jumping to
      specific rules as an if condition so complex rules can be established.
      
      This is only supported in GMAC5.10+.
      
      The following commands can be used to test this code:
      
      	1) Setup an ingress qdisk:
      	# tc qdisc add dev eth0 handle ffff: ingress
      
      	2) Setup a filter (e.g. filter by IP):
      	# tc filter add dev eth0 parent ffff: protocol ip u32 match ip \
      		src 192.168.0.3 skip_sw action drop
      
      In every tests performed we always used the "skip_sw" flag to make sure
      only the RX Parser was involved.
      Signed-off-by: default avatarJose Abreu <joabreu@synopsys.com>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Joao Pinto <jpinto@synopsys.com>
      Cc: Vitor Soares <soares@synopsys.com>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Cc: Jakub Kicinski <kubakici@wp.pl>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      4dbbe8dd
  6. 02 May, 2018 1 commit
  7. 23 Apr, 2018 1 commit
    • Jose Abreu's avatar
      net: stmmac: Implement logic to automatically select HW Interface · 5f0456b4
      Jose Abreu authored
      
      
      Move all the core version detection to a common place ("hwif.c") and
      implement a table which can be used to lookup the correct callbacks for
      each IP version.
      
      This simplifies the initialization flow of each IP version and eases
      future implementation of new IP versions.
      Signed-off-by: default avatarJose Abreu <joabreu@synopsys.com>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Joao Pinto <jpinto@synopsys.com>
      Cc: Vitor Soares <soares@synopsys.com>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      5f0456b4
  8. 19 Apr, 2018 1 commit
    • Jose Abreu's avatar
      net: stmmac: Disable ACS Feature for GMAC >= 4 · 565020aa
      Jose Abreu authored
      ACS Feature is currently enabled for GMAC >= 4 but the llc_snap status
      is never checked in descriptor rx_status callback. This will cause
      stmmac to always strip packets even that ACS feature is already
      stripping them.
      
      Lets be safe and disable the ACS feature for GMAC >= 4 and always strip
      the packets for this GMAC version.
      
      Fixes: 477286b5
      
       ("stmmac: add GMAC4 core support")
      Signed-off-by: default avatarJose Abreu <joabreu@synopsys.com>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Joao Pinto <jpinto@synopsys.com>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      565020aa
  9. 16 Apr, 2018 5 commits
  10. 30 Mar, 2018 2 commits
    • Jose Abreu's avatar
      net: stmmac: Add support for DWMAC5 and implement Safety Features · 8bf993a5
      Jose Abreu authored
      
      
      This adds initial suport for DWMAC5 and implements the Automotive Safety
      Package which is available from core version 5.10.
      
      The Automotive Safety Pacakge (also called Safety Features) offers us
      with error protection in the core by implementing ECC Protection in
      memories, on-chip data path parity protection, FSM parity and timeout
      protection and Application/CSR interface timeout protection.
      
      In case of an uncorrectable error we call stmmac_global_err() and
      reconfigure the whole core.
      Signed-off-by: default avatarJose Abreu <joabreu@synopsys.com>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Joao Pinto <jpinto@synopsys.com>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Cc: Andrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      8bf993a5
    • Jose Abreu's avatar
      net: stmmac: Rework and fix TX Timeout code · 34877a15
      Jose Abreu authored
      
      
      Currently TX Timeout handler does not behaves as expected and leads to
      an unrecoverable state. Rework current implementation of TX Timeout
      handling to actually perform a complete reset of the driver state and IP.
      
      We use deferred work to init a task which will be responsible for
      resetting the system.
      Signed-off-by: default avatarJose Abreu <joabreu@synopsys.com>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Joao Pinto <jpinto@synopsys.com>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Cc: Andrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      34877a15
  11. 26 Mar, 2018 1 commit
  12. 27 Feb, 2018 3 commits
    • Niklas Cassel's avatar
      net: stmmac: ensure that the device has released ownership before reading data · a6b25da5
      Niklas Cassel authored
      
      
      According to Documentation/memory-barriers.txt, we need to use a
      dma_rmb() after reading the status/own bit, to ensure that all
      descriptor fields are read after reading the own bit.
      
      This way, we ensure that the DMA engine is done with the DMA
      descriptor before we read the other descriptor fields, e.g. reading
      the tx hardware timestamp (if PTP is enabled).
      Signed-off-by: default avatarNiklas Cassel <niklas.cassel@axis.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      a6b25da5
    • Niklas Cassel's avatar
      net: stmmac: use correct barrier between coherent memory and MMIO · 95eb930a
      Niklas Cassel authored
      
      
      The last memory barrier in stmmac_xmit()/stmmac_tso_xmit() is placed
      between a coherent memory write and a MMIO write:
      
      The own bit is written in First Desc (TSO: MSS desc or First Desc).
      <barrier>
      The DMA engine is started by a write to the tx desc tail pointer/
      enable dma transmission register, i.e. a MMIO write.
      
      This barrier cannot be a simple dma_wmb(), since a dma_wmb() is only
      used to guarantee the ordering, with respect to other writes,
      to cache coherent DMA memory.
      
      To guarantee that the cache coherent memory writes have completed
      before we attempt to write to the cache incoherent MMIO region,
      we need to use the more heavyweight barrier wmb().
      Signed-off-by: default avatarNiklas Cassel <niklas.cassel@axis.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      95eb930a
    • Niklas Cassel's avatar
      net: stmmac: ensure that the MSS desc is the last desc to set the own bit · 15d2ee42
      Niklas Cassel authored
      
      
      A dma_wmb() is used to guarantee the ordering, with respect to
      other writes, to cache coherent DMA memory.
      
      There is a dma_wmb() in prepare_tx_desc()/prepare_tso_tx_desc() which
      ensures that TDES0/1/2 is written before TDES3 (which contains the own
      bit), for First Desc.
      
      However, in the rare case that MSS changes, there will be a MSS
      context descriptor in front of the regular DMA descriptors:
      
      <MSS desc> <- DMA Next Descriptor
      <First Desc>
      <desc n>
      <Last Desc>
      
      Thus, for this special case, we need a dma_wmb()
      after prepare_tso_tx_desc()/before writing the own bit to the MSS desc,
      so that we flush the write to TDES3 for First Desc,
      in order to ensure that the MSS descriptor is the last descriptor to
      set the own bit.
      Signed-off-by: default avatarNiklas Cassel <niklas.cassel@axis.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      15d2ee42
  13. 20 Feb, 2018 4 commits
  14. 22 Jan, 2018 1 commit
    • Florian Fainelli's avatar
      net: stmmac: Fix reception of Broadcom switches tags · 8cad443e
      Florian Fainelli authored
      
      
      Broadcom tags inserted by Broadcom switches put a 4 byte header after
      the MAC SA and before the EtherType, which may look like some sort of 0
      length LLC/SNAP packet (tcpdump and wireshark do think that way). With
      ACS enabled in stmmac the packets were truncated to 8 bytes on
      reception, whereas clearing this bit allowed normal reception to occur.
      
      In order to make that possible, we need to pass a net_device argument to
      the different core_init() functions and we are dependent on the Broadcom
      tagger padding packets correctly (which it now does). To be as little
      invasive as possible, this is only done for gmac1000 when the network
      device is DSA-enabled (netdev_uses_dsa() returns true).
      Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Acked-by: default avatarGiuseppe Cavallaro <peppe.cavallaro@st.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      8cad443e
  15. 04 Jan, 2018 1 commit
  16. 03 Jan, 2018 1 commit
  17. 19 Dec, 2017 1 commit
  18. 08 Dec, 2017 1 commit
    • Niklas Cassel's avatar
      net: stmmac: fix broken dma_interrupt handling for multi-queues · 5a6a0445
      Niklas Cassel authored
      There is nothing that says that number of TX queues == number of RX
      queues. E.g. the ARTPEC-6 SoC has 2 TX queues and 1 RX queue.
      
      This code is obviously wrong:
      for (chan = 0; chan < tx_channel_count; chan++) {
          struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
      
      priv->rx_queue has size MTL_MAX_RX_QUEUES, so this will send an
      uninitialized napi_struct to __napi_schedule(), causing us to
      crash in net_rx_action(), because napi_struct->poll is zero.
      
      [12846.759880] Unable to handle kernel NULL pointer dereference at virtual address 00000000
      [12846.768014] pgd = (ptrval)
      [12846.770742] [00000000] *pgd=39ec7831, *pte=00000000, *ppte=00000000
      [12846.777023] Internal error: Oops: 80000007 [#1] PREEMPT SMP ARM
      [12846.782942] Modules linked in:
      [12846.785998] CPU: 0 PID: 161 Comm: dropbear Not tainted 4.15.0-rc2-00285-gf5fb5f2f39a7 #36
      [12846.794177] Hardware name: Axis ARTPEC-6 Platform
      [12846.798879] task: (ptrval) task.stack: (ptrval)
      [12846.803407] PC is at 0x0
      [12846.805942] LR is at net_rx_action+0x274/0x43c
      [12846.810383] pc : [<00000000>]    lr : [<80bff064>]    psr: 200e0113
      [12846.816648] sp : b90d9ae8  ip : b90d9ae8  fp : b90d9b44
      [12846.821871] r10: 00000008  r9 : 0013250e  r8 : 00000100
      [12846.827094] r7 : 0000012c  r6 : 00000000  r5 : 00000001  r4 : bac84900
      [12846.833619] r3 : 00000000  r2 : b90d9b08  r1 : 00000000  r0 : bac84900
      
      Since each DMA channel can be used for rx and tx simultaneously,
      the current code should probably be rewritten so that napi_struct is
      embedded in a new struct stmmac_channel.
      That way, stmmac_poll() can call stmmac_tx_clean() on just the tx queue
      where we got the IRQ, instead of looping through all tx queues.
      This is also how the xgbe driver does it (another driver for this IP).
      
      Fixes: c22a3f48
      
       ("net: stmmac: adding multiple napi mechanism")
      Signed-off-by: default avatarNiklas Cassel <niklas.cassel@axis.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      5a6a0445
  19. 03 Dec, 2017 1 commit
    • Lars Persson's avatar
      stmmac: reset last TSO segment size after device open · 45ab4b13
      Lars Persson authored
      The mss variable tracks the last max segment size sent to the TSO
      engine. We do not update the hardware as long as we receive skb:s with
      the same value in gso_size.
      
      During a network device down/up cycle (mapped to stmmac_release() and
      stmmac_open() callbacks) we issue a reset to the hardware and it
      forgets the setting for mss. However we did not zero out our mss
      variable so the next transmission of a gso packet happens with an
      undefined hardware setting.
      
      This triggers a hang in the TSO engine and eventuelly the netdev
      watchdog will bark.
      
      Fixes: f748be53
      
       ("stmmac: support new GMAC4")
      Signed-off-by: default avatarLars Persson <larper@axis.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      45ab4b13