- 30 May, 2018 1 commit
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Evan Quan authored
The AMD_CG_SUPPORT_HDP_LS was wrongly written as AMD_CG_SUPPORT_BIF_LS. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 24 May, 2018 2 commits
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Rex Zhu authored
Enable static VCN powergating by default on Raven. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
Enable VCN clockgating by default on Raven. Reviewed-by:
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- 18 May, 2018 4 commits
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Feifei Xu authored
v2: fix whitespace (Alex) Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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James Zhu authored
Vega20 ucode load type is set to AMDGPU_FW_LOAD_DIRECT for default. So UVD/VCE needn't PSP IP block up. UVD/VCE for Vega20 can be enabled at this moment. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Feifei Xu authored
Please enable above ips on soc15.c when they're available. Reviewed-by:
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Evan Quan authored
v2: remove duplicate flag. Reviewed-by:
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- 17 May, 2018 6 commits
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Feifei Xu authored
Some register offset in nbio v7.4 are different with v7.0. v2: Use nbio7.0 for now. TODO: add a new nbio 7.4 module (Alex) Signed-off-by:
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Feifei Xu authored
Same as vega10 now. v2: squash in typo fix Reviewed-by:
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Feifei Xu authored
Vega20 need a seperate vega20_reg_init.c due to ip base offset difference. Reviewed-by:
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Feifei Xu authored
Same as vega10 for now. Reviewed-by:
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Feifei Xu authored
Set external_rev_id and disable cg,pg for now. Reviewed-by:
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Feifei Xu authored
Signed-off-by:
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- 15 May, 2018 2 commits
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Huang Rui authored
Signed-off-by:
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Alex Deucher authored
Userspace needs to query this value to work around a hw bug in certain cases. Acked-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by:
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- 11 Apr, 2018 2 commits
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Alex Deucher authored
Used to check on a per SoC basis whether the SoC needs a full reset of a per IP soft reset. Reviewed-by:
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Hawking Zhang authored
Signed-off-by:
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- 21 Mar, 2018 4 commits
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Hawking Zhang authored
Initialize the IP offsets for vega12. Acked-by:
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Feifei Xu authored
Add external_rev_id for vega12. Acked-by:
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Evan Quan authored
Add the appropriate clockgating flags for vega12 Acked-by:
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Alex Deucher authored
Add the IP blocks, clock and powergating flags, and common clockgating support. Acked-by:
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- 19 Mar, 2018 1 commit
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Rex Zhu authored
Reviewed-by:
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- 15 Mar, 2018 1 commit
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Rex Zhu authored
1. delete amdgpu_powerplay.c used for wrapping smu ip functions 2. delete struct pp_instance, 3. make struct hwmgr as the smu hw handle. Reviewed-by:
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- 14 Mar, 2018 4 commits
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Alex Deucher authored
No need to replicate it in several places. Reviewed-by:
Rex Zhu <rezhu@amd.com> Acked-by:
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Alex Deucher authored
Regardless of whether the user has selected psp fw loading or not. It's still needed for GPU reset among other things. There are already guards in place to avoid setting up the full psp if PSP fw loading is not enabled. Reviewed-by:
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Alex Deucher authored
The per device firmware load method is limited to what makes sense for that asic rather than whatever arbitrary value may have been set by the user. Reviewed-by:
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Alex Deucher authored
No need to replicate it in several places. Reviewed-by:
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- 19 Feb, 2018 3 commits
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Alex Deucher authored
The IP soft reset interface is for per IP reset but it was being abused for adapter reset on soc15 asics. Adjust the interface to make it explicit. Reviewed-by:
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Christian König authored
This adds an optional ring to the invalidate_hdp and flush_hdp callbacks. If the ring isn't specified or the emit_wreg function not available the HDP operation will be done with the CPU otherwise by writing on the ring. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Alex Deucher authored
Needed to flush and invalidate the HDP block using the CPU. v2: use preferred register on soc15. Reviewed-by:
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- 19 Jan, 2018 1 commit
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Huang Rui authored
MMHUB power gating still has issue, and doesn't work on raven at current. So disable it for the moment. Signed-off-by:
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- 18 Dec, 2017 2 commits
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Alex Deucher authored
add device to the name for consistency. Acked-by:
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Alex Deucher authored
add device to the name for consistency. Acked-by:
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- 13 Dec, 2017 2 commits
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Alex Deucher authored
The golden register arrays were empty so the function was effectively useless. Acked-by:
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Alex Deucher authored
Cleans up and consolidates all of the per-asic logic. v2: squash in "drm/amdgpu: fix NULL err for sriov detect" (Chunming) Acked-by:
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- 08 Dec, 2017 4 commits
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Shaoyun Liu authored
Remove the header where it's not used. Acked-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by:
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Shaoyun Liu authored
Acked-by:
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Shaoyun Liu authored
Handle dynamic offsets correctly in static arrays. Acked-by:
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Shaoyun Liu authored
The base offsets of the IP blocks may change across asics even though the relative register offsets are the same for an IP. Handle this dynamically. Acked-by:
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- 06 Dec, 2017 1 commit
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Feifei Xu authored
Remove asic_reg/vega10 folder. Signed-off-by:
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