• David S. Miller's avatar
    [SPARC64]: Add PCI MSI support on Niagara. · 35a17eb6
    David S. Miller authored
    This is kind of hokey, we could use the hardware provided facilities
    much better.
    MSIs are assosciated with MSI Queues.  MSI Queues generate interrupts
    when any MSI assosciated with it is signalled.  This suggests a
    two-tiered IRQ dispatch scheme:
    	MSI Queue interrupt --> queue interrupt handler
    		MSI dispatch --> driver interrupt handler
    But we just get one-level under Linux currently.  What I'd like to do
    is possibly stick the IRQ actions into a per-MSI-Queue data structure,
    and dispatch them form there, but the generic IRQ layer doesn't
    provide a way to do that right now.
    So, the current kludge is to "ACK" the interrupt by processing the
    MSI Queue data structures and ACK'ing them, then we run the actual
    handler like normal.
    We are wasting a lot of useful information, for example the MSI data
    and address are provided with ever MSI, as well as a system tick if
    available.  If we could pass this into the IRQ handler it could help
    with certain things, in particular for PCI-Express error messages.
    The MSI entries on sparc64 also tell you exactly which bus/device/fn
    sent the MSI, which would be great for error handling when no
    registered IRQ handler can service the interrupt.
    We override the disable/enable IRQ chip methods in sun4v_msi, so we
    have to call {mask,unmask}_msi_irq() directly from there.  This is
    another ugly wart.
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>