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Commit 9e857a40 authored by Andrew Lunn's avatar Andrew Lunn Committed by David S. Miller
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net: phy: Add missing features to PHY drivers

The bcm87xx and micrel driver has PHYs which are missing the .features
value. Add them. The bcm87xx is a 10G FEC only PHY. Add the needed
features definition of this PHY.

Fixes: 719655a1

 ("net: phy: Replace phy driver features u32 with link_mode bitmap")
Reported-by: default avatarScott Wood <oss@buserror.net>
Reported-by: default avatarCamelia Groza <camelia.groza@nxp.com>
Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a5a82d84
...@@ -197,6 +197,7 @@ static struct phy_driver bcm87xx_driver[] = { ...@@ -197,6 +197,7 @@ static struct phy_driver bcm87xx_driver[] = {
.phy_id = PHY_ID_BCM8706, .phy_id = PHY_ID_BCM8706,
.phy_id_mask = 0xffffffff, .phy_id_mask = 0xffffffff,
.name = "Broadcom BCM8706", .name = "Broadcom BCM8706",
.features = PHY_10GBIT_FEC_FEATURES,
.config_init = bcm87xx_config_init, .config_init = bcm87xx_config_init,
.config_aneg = bcm87xx_config_aneg, .config_aneg = bcm87xx_config_aneg,
.read_status = bcm87xx_read_status, .read_status = bcm87xx_read_status,
...@@ -208,6 +209,7 @@ static struct phy_driver bcm87xx_driver[] = { ...@@ -208,6 +209,7 @@ static struct phy_driver bcm87xx_driver[] = {
.phy_id = PHY_ID_BCM8727, .phy_id = PHY_ID_BCM8727,
.phy_id_mask = 0xffffffff, .phy_id_mask = 0xffffffff,
.name = "Broadcom BCM8727", .name = "Broadcom BCM8727",
.features = PHY_10GBIT_FEC_FEATURES,
.config_init = bcm87xx_config_init, .config_init = bcm87xx_config_init,
.config_aneg = bcm87xx_config_aneg, .config_aneg = bcm87xx_config_aneg,
.read_status = bcm87xx_read_status, .read_status = bcm87xx_read_status,
......
...@@ -1099,6 +1099,7 @@ static struct phy_driver ksphy_driver[] = { ...@@ -1099,6 +1099,7 @@ static struct phy_driver ksphy_driver[] = {
.phy_id = PHY_ID_KSZ8873MLL, .phy_id = PHY_ID_KSZ8873MLL,
.phy_id_mask = MICREL_PHY_ID_MASK, .phy_id_mask = MICREL_PHY_ID_MASK,
.name = "Micrel KSZ8873MLL Switch", .name = "Micrel KSZ8873MLL Switch",
.features = PHY_BASIC_FEATURES,
.config_init = kszphy_config_init, .config_init = kszphy_config_init,
.config_aneg = ksz8873mll_config_aneg, .config_aneg = ksz8873mll_config_aneg,
.read_status = ksz8873mll_read_status, .read_status = ksz8873mll_read_status,
......
...@@ -61,6 +61,9 @@ EXPORT_SYMBOL_GPL(phy_gbit_all_ports_features); ...@@ -61,6 +61,9 @@ EXPORT_SYMBOL_GPL(phy_gbit_all_ports_features);
__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init; __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init;
EXPORT_SYMBOL_GPL(phy_10gbit_features); EXPORT_SYMBOL_GPL(phy_10gbit_features);
__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_fec_features) __ro_after_init;
EXPORT_SYMBOL_GPL(phy_10gbit_fec_features);
static const int phy_basic_ports_array[] = { static const int phy_basic_ports_array[] = {
ETHTOOL_LINK_MODE_Autoneg_BIT, ETHTOOL_LINK_MODE_Autoneg_BIT,
ETHTOOL_LINK_MODE_TP_BIT, ETHTOOL_LINK_MODE_TP_BIT,
...@@ -109,6 +112,11 @@ const int phy_10gbit_features_array[1] = { ...@@ -109,6 +112,11 @@ const int phy_10gbit_features_array[1] = {
}; };
EXPORT_SYMBOL_GPL(phy_10gbit_features_array); EXPORT_SYMBOL_GPL(phy_10gbit_features_array);
const int phy_10gbit_fec_features_array[1] = {
ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
};
EXPORT_SYMBOL_GPL(phy_10gbit_fec_features_array);
__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init; __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init;
EXPORT_SYMBOL_GPL(phy_10gbit_full_features); EXPORT_SYMBOL_GPL(phy_10gbit_full_features);
...@@ -191,6 +199,10 @@ static void features_init(void) ...@@ -191,6 +199,10 @@ static void features_init(void)
linkmode_set_bit_array(phy_10gbit_full_features_array, linkmode_set_bit_array(phy_10gbit_full_features_array,
ARRAY_SIZE(phy_10gbit_full_features_array), ARRAY_SIZE(phy_10gbit_full_features_array),
phy_10gbit_full_features); phy_10gbit_full_features);
/* 10G FEC only */
linkmode_set_bit_array(phy_10gbit_fec_features_array,
ARRAY_SIZE(phy_10gbit_fec_features_array),
phy_10gbit_fec_features);
} }
void phy_device_free(struct phy_device *phydev) void phy_device_free(struct phy_device *phydev)
......
...@@ -48,6 +48,7 @@ extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init; ...@@ -48,6 +48,7 @@ extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;
extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init; extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init;
extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init; extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init;
extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init; extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init;
extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_fec_features) __ro_after_init;
extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init; extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init;
#define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features) #define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features)
...@@ -56,6 +57,7 @@ extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_ini ...@@ -56,6 +57,7 @@ extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_ini
#define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features) #define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features)
#define PHY_GBIT_ALL_PORTS_FEATURES ((unsigned long *)&phy_gbit_all_ports_features) #define PHY_GBIT_ALL_PORTS_FEATURES ((unsigned long *)&phy_gbit_all_ports_features)
#define PHY_10GBIT_FEATURES ((unsigned long *)&phy_10gbit_features) #define PHY_10GBIT_FEATURES ((unsigned long *)&phy_10gbit_features)
#define PHY_10GBIT_FEC_FEATURES ((unsigned long *)&phy_10gbit_fec_features)
#define PHY_10GBIT_FULL_FEATURES ((unsigned long *)&phy_10gbit_full_features) #define PHY_10GBIT_FULL_FEATURES ((unsigned long *)&phy_10gbit_full_features)
extern const int phy_10_100_features_array[4]; extern const int phy_10_100_features_array[4];
......
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