1. 23 Nov, 2014 7 commits
    • Thomas Gleixner's avatar
      PCI/MSI: Rename mask/unmask_msi_irq treewide · 280510f1
      Thomas Gleixner authored
      
      
      The PCI/MSI irq chip callbacks mask/unmask_msi_irq have been renamed
      to pci_msi_mask/unmask_irq to mark them PCI specific. Rename all usage
      sites. The conversion helper functions are kept around to avoid
      conflicts in next and will be removed after merging into mainline.
      
      Coccinelle assisted conversion. No functional change.
      
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: Chris Metcalf <cmetcalf@tilera.com>
      Cc: x86@kernel.org
      Cc: Jiang Liu <jiang.liu@linux.intel.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Murali Karicheri <m-karicheri2@ti.com>
      Cc: Thierry Reding <thierry.reding@gmail.com>
      Cc: Mohit Kumar <mohit.kumar@st.com>
      Cc: Simon Horman <horms@verge.net.au>
      Cc: Michal Simek <michal.simek@xilinx.com>
      Cc: Yijing Wang <wangyijing@huawei.com>
      280510f1
    • Thomas Gleixner's avatar
      PCI/MSI: Rename mask/unmask_msi_irq et al · 23ed8d57
      Thomas Gleixner authored
      
      
      mask/unmask_msi_irq and __mask_msi/msix_irq are PCI/MSI specific
      functions and should be named accordingly. This is a preparatory patch
      to support MSI on non PCI devices.
      
      Rename mask/unmask_msi_irq to pci_msi_mask/unmask_irq and document the
      functions. Provide conversion helpers.
      
      Rename __mask_msi/msix_irq to __pci_msi/msix_desc_mask so its clear
      that they operated on msi_desc. Fixup the only user outside of
      pci/msi.
      
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Jiang Liu <jiang.liu@linux.intel.com>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Yijing Wang <wangyijing@huawei.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      23ed8d57
    • Jiang Liu's avatar
      PCI/MSI: Rename write_msi_msg() to pci_write_msi_msg() · 83a18912
      Jiang Liu authored
      
      
      Rename write_msi_msg() to pci_write_msi_msg() to mark it as PCI
      specific.
      
      Signed-off-by: default avatarJiang Liu <jiang.liu@linux.intel.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Yingjoe Chen <yingjoe.chen@mediatek.com>
      Cc: Yijing Wang <wangyijing@huawei.com>
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      83a18912
    • Jiang Liu's avatar
      PCI/MSI: Rename __read_msi_msg() to __pci_read_msi_msg() · 891d4a48
      Jiang Liu authored
      
      
      Rename __read_msi_msg() to __pci_read_msi_msg() and kill unused
      read_msi_msg(). It's a preparation to separate generic MSI code from
      PCI core.
      
      Signed-off-by: default avatarJiang Liu <jiang.liu@linux.intel.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Yingjoe Chen <yingjoe.chen@mediatek.com>
      Cc: Yijing Wang <wangyijing@huawei.com>
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      891d4a48
    • Jiang Liu's avatar
      PCI/MSI: Kill redundant call of irq_set_msi_desc() for MSI-X interrupts · d71d6432
      Jiang Liu authored
      
      
      It is the repsonsibility of arch_setup_msi_irq()/arch_setup_msi_irqs()
      to call irq_set_msi_desc() to associate IRQ descriptors and MSI
      descriptors. Kill the redundant call of irq_set_msi_desc() for MSI-X
      interrupts in the PCI MSI core.
      
      Signed-off-by: default avatarJiang Liu <jiang.liu@linux.intel.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Yingjoe Chen <yingjoe.chen@mediatek.com>
      Cc: Yijing Wang <wangyijing@huawei.com>
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      d71d6432
    • Jiang Liu's avatar
      PCI/MSI: Simplify PCI MSI code by initializing msi_desc.nvec_used earlier · 63a7b17e
      Jiang Liu authored
      
      
      Simplify PCI MSI code by initializing msi_desc.nvec_used and
      msi_desc.msi_attrib.multiple when creating MSI descriptors.
      
      Also remove redundant checks in IRQ remapping drivers, PCI MSI core
      already guarantees these.
      
      Signed-off-by: default avatarJiang Liu <jiang.liu@linux.intel.com>
      Acked-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Yingjoe Chen <yingjoe.chen@mediatek.com>
      Cc: Yijing Wang <wangyijing@huawei.com>
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      63a7b17e
    • Jiang Liu's avatar
      PCI/MSI: Remove unnecessary braces around single statements · 3f3cecae
      Jiang Liu authored
      
      
      Per Documentation/CodingStyle, don't use braces around single statements.
      
      Signed-off-by: default avatarJiang Liu <jiang.liu@linux.intel.com>
      Acked-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Yingjoe Chen <yingjoe.chen@mediatek.com>
      Cc: Yijing Wang <wangyijing@huawei.com>
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      3f3cecae
  2. 21 Nov, 2014 5 commits
  3. 12 Nov, 2014 2 commits
  4. 11 Nov, 2014 1 commit
  5. 06 Nov, 2014 1 commit
    • Yijing Wang's avatar
      PCI/MSI: Add pci_msi_ignore_mask to prevent writes to MSI/MSI-X Mask Bits · 38737d82
      Yijing Wang authored
      MSI-X vector Mask Bits are in MSI-X Tables in PCI memory space.  Xen PV
      guests can't write to those tables.  MSI vector Mask Bits are in PCI
      configuration space.  Xen PV guests can write to config space, but those
      writes are ignored.
      
      Commit 0e4ccb15
      
       ("PCI: Add x86_msi.msi_mask_irq() and
      msix_mask_irq()") added a way to override default_mask_msi_irqs() and
      default_mask_msix_irqs() so they can be no-ops in Xen guests, but this is
      more complicated than necessary.
      
      Add "pci_msi_ignore_mask" in the core PCI MSI code.  If set,
      default_mask_msi_irqs() and default_mask_msix_irqs() return without doing
      anything.  This is less flexible, but much simpler.
      
      [bhelgaas: changelog]
      Signed-off-by: default avatarYijing Wang <wangyijing@huawei.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: default avatarDavid Vrabel <david.vrabel@citrix.com>
      CC: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      CC: xen-devel@lists.xenproject.org
      38737d82
  6. 06 Oct, 2014 1 commit
  7. 02 Oct, 2014 1 commit
  8. 01 Oct, 2014 10 commits
  9. 30 Sep, 2014 6 commits
    • Liviu Dudau's avatar
      PCI: Add pci_remap_iospace() to map bus I/O resources · 8b921acf
      Liviu Dudau authored
      
      
      Add pci_remap_iospace() to map bus I/O resources into the CPU virtual
      address space.  Architectures with special needs may provide their own
      version, but most should be able to use this one.
      
      This function is useful for PCI host bridge drivers that need to map the
      PCI I/O resources into virtual memory space.
      
      [bhelgaas: phys_addr description, drop temporary "err" variable]
      Signed-off-by: Liviu Dudau's avatarLiviu Dudau <Liviu.Dudau@arm.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: default avatarRob Herring <robh@kernel.org>
      Reviewed-by: Catalin Marinas's avatarCatalin Marinas <catalin.marinas@arm.com>
      CC: Arnd Bergmann <arnd@arndb.de>
      8b921acf
    • Liviu Dudau's avatar
      of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr() · 41e5c0f8
      Liviu Dudau authored
      
      
      Add pci_get_new_domain_nr() to allocate a new domain number and
      of_get_pci_domain_nr() to retrieve the PCI domain number of a given device
      from DT.  Host bridge drivers or architecture-specific code can choose to
      implement their PCI domain number policy using these two functions.
      
      Using of_get_pci_domain_nr() guarantees a stable PCI domain number on every
      boot provided that all host bridge controllers are assigned a number in the
      device tree using "linux,pci-domain" property.  Mixing use of
      pci_get_new_domain_nr() and of_get_pci_domain_nr() is not recommended as it
      can lead to potentially conflicting domain numbers being assigned to root
      buses behind different host bridges.
      
      Signed-off-by: Liviu Dudau's avatarLiviu Dudau <Liviu.Dudau@arm.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      CC: Arnd Bergmann <arnd@arndb.de>
      CC: Grant Likely <grant.likely@linaro.org>
      CC: Rob Herring <robh+dt@kernel.org>
      CC: Catalin Marinas <catalin.marinas@arm.com>
      41e5c0f8
    • Catalin Marinas's avatar
      PCI: Add generic domain handling · 670ba0c8
      Catalin Marinas authored
      
      
      The handling of PCI domains (or PCI segments in ACPI speak) is usually a
      straightforward affair but its implementation is currently left to the
      architectural code, with pci_domain_nr(b) querying the value of the domain
      associated with bus b.
      
      This patch introduces CONFIG_PCI_DOMAINS_GENERIC as an option that can be
      selected if an architecture wants a simple implementation where the value
      of the domain associated with a bus is stored in struct pci_bus.
      
      The architectures that select CONFIG_PCI_DOMAINS_GENERIC will then have to
      implement pci_bus_assign_domain_nr() as a way of setting the domain number
      associated with a root bus.  All child buses except the root bus will
      inherit the domain_nr value from their parent.
      
      Signed-off-by: Catalin Marinas's avatarCatalin Marinas <Catalin.Marinas@arm.com>
      [Renamed pci_set_domain_nr() to pci_bus_assign_domain_nr()]
      Signed-off-by: Liviu Dudau's avatarLiviu Dudau <Liviu.Dudau@arm.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      CC: Arnd Bergmann <arnd@arndb.de>
      670ba0c8
    • Liviu Dudau's avatar
      of/pci: Fix the conversion of IO ranges into IO resources · 0b0b0893
      Liviu Dudau authored
      
      
      The ranges property for a host bridge controller in DT describes the
      mapping between the PCI bus address and the CPU physical address.  The
      resources framework however expects that the IO resources start at a pseudo
      "port" address 0 (zero) and have a maximum size of IO_SPACE_LIMIT.  The
      conversion from PCI ranges to resources failed to take that into account,
      returning a CPU physical address instead of a port number.
      
      Also fix all the drivers that depend on the old behaviour by fetching the
      CPU physical address based on the port number where it is being needed.
      
      Signed-off-by: Liviu Dudau's avatarLiviu Dudau <Liviu.Dudau@arm.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      CC: Grant Likely <grant.likely@linaro.org>
      CC: Rob Herring <robh+dt@kernel.org>
      CC: Arnd Bergmann <arnd@arndb.de>
      CC: Thierry Reding <thierry.reding@gmail.com>
      CC: Simon Horman <horms@verge.net.au>
      CC: Catalin Marinas <catalin.marinas@arm.com>
      0b0b0893
    • Lucas Stach's avatar
      PCI: designware: Setup and clear exactly one MSI at a time · 91f8ae82
      Lucas Stach authored
      
      
      The setup_irq function is supposed to set up exactly one MSI IRQ.  Multiple
      IRQ setup is handled differently, to respect the choices made by the upper
      layers.
      
      Also only clear one MSI IRQ at a time; the PCI core will call into this
      function multiple times if it has to tear down more than one MSI IRQ.
      
      Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: default avatarPratyush Anand <pratyush.anand@st.com>
      Acked-by: default avatarJingoo Han <jg1.han@samsung.com>
      91f8ae82
    • Yinghai Lu's avatar
      PCI: Add missing MEM_64 mask in pci_assign_unassigned_bridge_resources() · d61b0e87
      Yinghai Lu authored
      In 5b285415 ("PCI: Restrict 64-bit prefetchable bridge windows to
      64-bit resources"), we added IORESOURCE_MEM_64 to the mask in
      pci_assign_unassigned_root_bus_resources(), but not to the mask in
      pci_assign_unassigned_bridge_resources().
      
      Add IORESOURCE_MEM_64 to the pci_assign_unassigned_bridge_resources() type
      mask.
      
      Fixes: 5b285415
      
       ("PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources")
      Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      CC: stable@vger.kernel.org	# v3.16+
      d61b0e87
  10. 29 Sep, 2014 2 commits
  11. 25 Sep, 2014 1 commit
  12. 24 Sep, 2014 3 commits