- 06 Jun, 2017 1 commit
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Jiri Pirko authored
The "trap_id" is 9bits long. So far, this was not a problem since we used only traps with ids that fit into 8bits. But the ACL traps that are going to be introduced use the 9th bit. Fixes: eda6500a ("mlxsw: Add PCI bus implementation") Signed-off-by:
Jiri Pirko <jiri@mellanox.com> Reviewed-by:
Yotam Gigi <yotamg@mellanox.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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- 12 Jan, 2017 1 commit
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Elad Raz authored
The event_data starts from address 0x00-0x0C and not from 0x08-0x014. This leads to duplication with other fields in the Event Queue Element such as sub-type, cqn and owner. Fixes: eda6500a ("mlxsw: Add PCI bus implementation") Signed-off-by:
Elad Raz <eladr@mellanox.com> Signed-off-by:
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- 03 Nov, 2016 1 commit
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Elad Raz authored
The system-status register is actually 16-bit wide and not 8 bit-wide. Fixes: 233fa44b ("mlxsw: pci: Implement reset done check") Signed-off-by:
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- 28 Oct, 2016 2 commits
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Jiri Pirko authored
So far, mlxsw_pci.ko is the module that registers PCI table for all drivers (spectrum and switchx2). That is problematic for example with dracut. Since mlxsw_spectrum.ko and mlxsw_switchx2.ko are loaded dynamically from within mlxsw_core.ko, dracut does not have track of them and avoids them from being included in initramfs. So make this in an ordinary way and define the PCI tables in individual driver modules, so it can be properly loaded and included in dracut initramfs image. As a side effect, this patch could remove no longer necessary driver "kind" strings which were used to link PCI ids with individual mlxsw drivers. Suggested-by:
Ivan Vecera <ivecera@redhat.com> Tested-by:
Ido Schimmel <idosch@mellanox.com> Acked-by:
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Jiri Pirko authored
pci.h needs to be used for inner function declarations. So move the original one to more appropriate name, pci_hw.h. Signed-off-by:
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- 14 Mar, 2016 1 commit
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Jiri Pirko authored
Firmware now tells us that the reset is done by passing a magic value via register. Use it to shorten the wait in case this is supported. With old firmware, we still wait until the timeout is reached. Signed-off-by:
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- 03 Dec, 2015 1 commit
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Jiri Pirko authored
Completion queue element for receive queue provides information if the packet was received via LAG port. Extract this info and pass it along to core. Signed-off-by:
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- 16 Oct, 2015 3 commits
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Jiri Pirko authored
Add support for new generation Mellanox Spectrum ASIC, 10/25/40/50 and 100Gb/s Ethernet Switch. The initial driver implements bridge forwarding offload including bridge internal VLAN support, FDB static entries, FDB learning and HW ageing including their setup. Signed-off-by:
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Jiri Pirko authored
Remove strict number check of queues count as various ASICs have different counts. Signed-off-by:
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Jiri Pirko authored
The count of CQs can be different for various ASICs, so just define maximal value and check for that. Signed-off-by:
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- 10 Aug, 2015 1 commit
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Jiri Pirko authored
FCS of incoming packets is already checked by HW. Just strip it out. Signed-off-by:
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- 30 Jul, 2015 2 commits
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Jiri Pirko authored
Benefit from the previously introduced Mellanox Switch infrastructure and add driver for SwitchX-2 ASIC. Note that this driver is very simple now. It implements bare minimum for getting device to work on slow-path. Fast-path offload functionality is going to be added soon. Signed-off-by:
Scott Feldman <sfeldma@gmail.com> Signed-off-by:
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Jiri Pirko authored
Add PCI bus implementation for Mellanox Technologies Switch ASICs. This includes firmware initialization, async queues manipulation and command interface implementation. Signed-off-by:
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