micrel.c 29.9 KB
Newer Older
1
// SPDX-License-Identifier: GPL-2.0+
2
3
4
5
6
7
8
/*
 * drivers/net/phy/micrel.c
 *
 * Driver for Micrel PHYs
 *
 * Author: David J. Choi
 *
9
 * Copyright (c) 2010-2013 Micrel, Inc.
10
 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11
 *
12
 * Support : Micrel Phys:
13
 *		Giga phys: ksz9021, ksz9031, ksz9131
14
15
16
17
18
 *		100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
 *			   ksz8021, ksz8031, ksz8051,
 *			   ksz8081, ksz8091,
 *			   ksz8061,
 *		Switch : ksz8873, ksz886x
19
 *			 ksz9477
20
21
22
23
24
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/phy.h>
25
#include <linux/micrel_phy.h>
26
#include <linux/of.h>
27
#include <linux/clk.h>
28

29
30
/* Operation Mode Strap Override */
#define MII_KSZPHY_OMSO				0x16
31
#define KSZPHY_OMSO_FACTORY_TEST		BIT(15)
Johan Hovold's avatar
Johan Hovold committed
32
#define KSZPHY_OMSO_B_CAST_OFF			BIT(9)
33
#define KSZPHY_OMSO_NAND_TREE_ON		BIT(5)
Johan Hovold's avatar
Johan Hovold committed
34
35
#define KSZPHY_OMSO_RMII_OVERRIDE		BIT(1)
#define KSZPHY_OMSO_MII_OVERRIDE		BIT(0)
36

Choi, David's avatar
Choi, David committed
37
38
/* general Interrupt control/status reg in vendor specific block. */
#define MII_KSZPHY_INTCS			0x1B
Johan Hovold's avatar
Johan Hovold committed
39
40
41
42
43
44
45
46
#define	KSZPHY_INTCS_JABBER			BIT(15)
#define	KSZPHY_INTCS_RECEIVE_ERR		BIT(14)
#define	KSZPHY_INTCS_PAGE_RECEIVE		BIT(13)
#define	KSZPHY_INTCS_PARELLEL			BIT(12)
#define	KSZPHY_INTCS_LINK_PARTNER_ACK		BIT(11)
#define	KSZPHY_INTCS_LINK_DOWN			BIT(10)
#define	KSZPHY_INTCS_REMOTE_FAULT		BIT(9)
#define	KSZPHY_INTCS_LINK_UP			BIT(8)
Choi, David's avatar
Choi, David committed
47
48
49
#define	KSZPHY_INTCS_ALL			(KSZPHY_INTCS_LINK_UP |\
						KSZPHY_INTCS_LINK_DOWN)

50
51
52
53
54
55
/* PHY Control 1 */
#define	MII_KSZPHY_CTRL_1			0x1e

/* PHY Control 2 / PHY Control (if no PHY Control 1) */
#define	MII_KSZPHY_CTRL_2			0x1f
#define	MII_KSZPHY_CTRL				MII_KSZPHY_CTRL_2
Choi, David's avatar
Choi, David committed
56
/* bitmap of PHY register to set interrupt mode */
Johan Hovold's avatar
Johan Hovold committed
57
#define KSZPHY_CTRL_INT_ACTIVE_HIGH		BIT(9)
58
#define KSZPHY_RMII_REF_CLK_SEL			BIT(7)
Choi, David's avatar
Choi, David committed
59

60
61
62
63
64
65
66
67
68
69
70
71
72
73
/* Write/read to/from extended registers */
#define MII_KSZPHY_EXTREG                       0x0b
#define KSZPHY_EXTREG_WRITE                     0x8000

#define MII_KSZPHY_EXTREG_WRITE                 0x0c
#define MII_KSZPHY_EXTREG_READ                  0x0d

/* Extended registers */
#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
#define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
#define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106

#define PS_TO_REG				200

74
75
76
77
78
79
80
81
82
83
84
struct kszphy_hw_stat {
	const char *string;
	u8 reg;
	u8 bits;
};

static struct kszphy_hw_stat kszphy_hw_stats[] = {
	{ "phy_receive_errors", 21, 16},
	{ "phy_idle_errors", 10, 8 },
};

85
86
struct kszphy_type {
	u32 led_mode_reg;
87
	u16 interrupt_level_mask;
88
	bool has_broadcast_disable;
89
	bool has_nand_tree_disable;
90
	bool has_rmii_ref_clk_sel;
91
92
93
94
};

struct kszphy_priv {
	const struct kszphy_type *type;
95
	int led_mode;
96
97
	bool rmii_ref_clk_sel;
	bool rmii_ref_clk_sel_val;
98
	u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
99
100
101
102
};

static const struct kszphy_type ksz8021_type = {
	.led_mode_reg		= MII_KSZPHY_CTRL_2,
103
	.has_broadcast_disable	= true,
104
	.has_nand_tree_disable	= true,
105
	.has_rmii_ref_clk_sel	= true,
106
107
108
109
110
111
112
113
};

static const struct kszphy_type ksz8041_type = {
	.led_mode_reg		= MII_KSZPHY_CTRL_1,
};

static const struct kszphy_type ksz8051_type = {
	.led_mode_reg		= MII_KSZPHY_CTRL_2,
114
	.has_nand_tree_disable	= true,
115
116
117
118
};

static const struct kszphy_type ksz8081_type = {
	.led_mode_reg		= MII_KSZPHY_CTRL_2,
119
	.has_broadcast_disable	= true,
120
	.has_nand_tree_disable	= true,
121
	.has_rmii_ref_clk_sel	= true,
122
123
};

124
125
126
127
128
129
130
131
static const struct kszphy_type ks8737_type = {
	.interrupt_level_mask	= BIT(14),
};

static const struct kszphy_type ksz9021_type = {
	.interrupt_level_mask	= BIT(14),
};

132
static int kszphy_extended_write(struct phy_device *phydev,
133
				u32 regnum, u16 val)
134
135
136
137
138
139
{
	phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
	return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
}

static int kszphy_extended_read(struct phy_device *phydev,
140
				u32 regnum)
141
142
143
144
145
{
	phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
	return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
}

Choi, David's avatar
Choi, David committed
146
147
148
149
150
151
152
153
154
155
156
157
static int kszphy_ack_interrupt(struct phy_device *phydev)
{
	/* bit[7..0] int status, which is a read and clear register. */
	int rc;

	rc = phy_read(phydev, MII_KSZPHY_INTCS);

	return (rc < 0) ? rc : 0;
}

static int kszphy_config_intr(struct phy_device *phydev)
{
158
159
160
	const struct kszphy_type *type = phydev->drv->driver_data;
	int temp;
	u16 mask;
Choi, David's avatar
Choi, David committed
161

162
163
164
165
	if (type && type->interrupt_level_mask)
		mask = type->interrupt_level_mask;
	else
		mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
Choi, David's avatar
Choi, David committed
166
167
168

	/* set the interrupt pin active low */
	temp = phy_read(phydev, MII_KSZPHY_CTRL);
169
170
	if (temp < 0)
		return temp;
171
	temp &= ~mask;
Choi, David's avatar
Choi, David committed
172
173
	phy_write(phydev, MII_KSZPHY_CTRL, temp);

174
175
176
177
178
	/* enable / disable interrupts */
	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
		temp = KSZPHY_INTCS_ALL;
	else
		temp = 0;
Choi, David's avatar
Choi, David committed
179

180
	return phy_write(phydev, MII_KSZPHY_INTCS, temp);
Choi, David's avatar
Choi, David committed
181
}
182

183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
{
	int ctrl;

	ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
	if (ctrl < 0)
		return ctrl;

	if (val)
		ctrl |= KSZPHY_RMII_REF_CLK_SEL;
	else
		ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;

	return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
}

199
static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
200
{
201
	int rc, temp, shift;
202

203
204
205
206
207
208
209
210
211
212
213
	switch (reg) {
	case MII_KSZPHY_CTRL_1:
		shift = 14;
		break;
	case MII_KSZPHY_CTRL_2:
		shift = 4;
		break;
	default:
		return -EINVAL;
	}

214
	temp = phy_read(phydev, reg);
215
216
217
218
	if (temp < 0) {
		rc = temp;
		goto out;
	}
219

220
	temp &= ~(3 << shift);
221
222
	temp |= val << shift;
	rc = phy_write(phydev, reg, temp);
223
224
out:
	if (rc < 0)
225
		phydev_err(phydev, "failed to set led mode\n");
226

227
	return rc;
228
229
}

230
231
232
233
234
235
236
237
238
239
240
241
242
243
/* Disable PHY address 0 as the broadcast address, so that it can be used as a
 * unique (non-broadcast) address on a shared bus.
 */
static int kszphy_broadcast_disable(struct phy_device *phydev)
{
	int ret;

	ret = phy_read(phydev, MII_KSZPHY_OMSO);
	if (ret < 0)
		goto out;

	ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
out:
	if (ret)
244
		phydev_err(phydev, "failed to disable broadcast address\n");
245
246
247
248

	return ret;
}

249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
static int kszphy_nand_tree_disable(struct phy_device *phydev)
{
	int ret;

	ret = phy_read(phydev, MII_KSZPHY_OMSO);
	if (ret < 0)
		goto out;

	if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
		return 0;

	ret = phy_write(phydev, MII_KSZPHY_OMSO,
			ret & ~KSZPHY_OMSO_NAND_TREE_ON);
out:
	if (ret)
264
		phydev_err(phydev, "failed to disable NAND tree mode\n");
265
266
267
268

	return ret;
}

269
270
/* Some config bits need to be set again on resume, handle them here. */
static int kszphy_config_reset(struct phy_device *phydev)
271
{
272
	struct kszphy_priv *priv = phydev->priv;
273
	int ret;
274

275
276
277
	if (priv->rmii_ref_clk_sel) {
		ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
		if (ret) {
278
279
			phydev_err(phydev,
				   "failed to set rmii reference clock\n");
280
281
282
283
			return ret;
		}
	}

284
	if (priv->led_mode >= 0)
285
		kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
286
287

	return 0;
288
289
}

290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
static int kszphy_config_init(struct phy_device *phydev)
{
	struct kszphy_priv *priv = phydev->priv;
	const struct kszphy_type *type;

	if (!priv)
		return 0;

	type = priv->type;

	if (type->has_broadcast_disable)
		kszphy_broadcast_disable(phydev);

	if (type->has_nand_tree_disable)
		kszphy_nand_tree_disable(phydev);

	return kszphy_config_reset(phydev);
}

309
310
static int ksz8041_config_init(struct phy_device *phydev)
{
311
312
	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };

313
314
315
316
317
	struct device_node *of_node = phydev->mdio.dev.of_node;

	/* Limit supported and advertised modes in fiber mode */
	if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
		phydev->dev_flags |= MICREL_PHY_FXEN;
318
319
320
321
322
323
324
325
326
		linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
		linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);

		linkmode_and(phydev->supported, phydev->supported, mask);
		linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
				 phydev->supported);
		linkmode_and(phydev->advertising, phydev->advertising, mask);
		linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
				 phydev->advertising);
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
		phydev->autoneg = AUTONEG_DISABLE;
	}

	return kszphy_config_init(phydev);
}

static int ksz8041_config_aneg(struct phy_device *phydev)
{
	/* Skip auto-negotiation in fiber mode */
	if (phydev->dev_flags & MICREL_PHY_FXEN) {
		phydev->speed = SPEED_100;
		return 0;
	}

	return genphy_config_aneg(phydev);
}

344
345
346
347
348
349
350
351
352
353
354
355
static int ksz8081_config_init(struct phy_device *phydev)
{
	/* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
	 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
	 * pull-down is missing, the factory test mode should be cleared by
	 * manually writing a 0.
	 */
	phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);

	return kszphy_config_init(phydev);
}

356
357
358
359
360
361
362
363
364
365
366
static int ksz8061_config_init(struct phy_device *phydev)
{
	int ret;

	ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
	if (ret)
		return ret;

	return kszphy_config_init(phydev);
}

367
static int ksz9021_load_values_from_of(struct phy_device *phydev,
368
369
370
371
				       const struct device_node *of_node,
				       u16 reg,
				       const char *field1, const char *field2,
				       const char *field3, const char *field4)
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
{
	int val1 = -1;
	int val2 = -2;
	int val3 = -3;
	int val4 = -4;
	int newval;
	int matches = 0;

	if (!of_property_read_u32(of_node, field1, &val1))
		matches++;

	if (!of_property_read_u32(of_node, field2, &val2))
		matches++;

	if (!of_property_read_u32(of_node, field3, &val3))
		matches++;

	if (!of_property_read_u32(of_node, field4, &val4))
		matches++;

	if (!matches)
		return 0;

	if (matches < 4)
		newval = kszphy_extended_read(phydev, reg);
	else
		newval = 0;

	if (val1 != -1)
		newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);

403
	if (val2 != -2)
404
405
		newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);

406
	if (val3 != -3)
407
408
		newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);

409
	if (val4 != -4)
410
411
412
413
414
415
416
		newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);

	return kszphy_extended_write(phydev, reg, newval);
}

static int ksz9021_config_init(struct phy_device *phydev)
{
417
	const struct device *dev = &phydev->mdio.dev;
418
	const struct device_node *of_node = dev->of_node;
419
420
421
422
423
424
	const struct device *dev_walker;

	/* The Micrel driver has a deprecated option to place phy OF
	 * properties in the MAC node. Walk up the tree of devices to
	 * find a device with an OF node.
	 */
425
	dev_walker = &phydev->mdio.dev;
426
427
428
429
430
	do {
		of_node = dev_walker->of_node;
		dev_walker = dev_walker->parent;

	} while (!of_node && dev_walker);
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448

	if (of_node) {
		ksz9021_load_values_from_of(phydev, of_node,
				    MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
				    "txen-skew-ps", "txc-skew-ps",
				    "rxdv-skew-ps", "rxc-skew-ps");
		ksz9021_load_values_from_of(phydev, of_node,
				    MII_KSZPHY_RX_DATA_PAD_SKEW,
				    "rxd0-skew-ps", "rxd1-skew-ps",
				    "rxd2-skew-ps", "rxd3-skew-ps");
		ksz9021_load_values_from_of(phydev, of_node,
				    MII_KSZPHY_TX_DATA_PAD_SKEW,
				    "txd0-skew-ps", "txd1-skew-ps",
				    "txd2-skew-ps", "txd3-skew-ps");
	}
	return 0;
}

449
450
451
#define KSZ9031_PS_TO_REG		60

/* Extended registers */
452
453
454
455
/* MMD Address 0x0 */
#define MII_KSZ9031RN_FLP_BURST_TX_LO	3
#define MII_KSZ9031RN_FLP_BURST_TX_HI	4

456
/* MMD Address 0x2 */
457
458
459
460
461
#define MII_KSZ9031RN_CONTROL_PAD_SKEW	4
#define MII_KSZ9031RN_RX_DATA_PAD_SKEW	5
#define MII_KSZ9031RN_TX_DATA_PAD_SKEW	6
#define MII_KSZ9031RN_CLK_PAD_SKEW	8

462
463
464
465
/* MMD Address 0x1C */
#define MII_KSZ9031RN_EDPD		0x23
#define MII_KSZ9031RN_EDPD_ENABLE	BIT(0)

466
static int ksz9031_of_load_skew_values(struct phy_device *phydev,
467
				       const struct device_node *of_node,
468
				       u16 reg, size_t field_sz,
469
				       const char *field[], u8 numfields)
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
{
	int val[4] = {-1, -2, -3, -4};
	int matches = 0;
	u16 mask;
	u16 maxval;
	u16 newval;
	int i;

	for (i = 0; i < numfields; i++)
		if (!of_property_read_u32(of_node, field[i], val + i))
			matches++;

	if (!matches)
		return 0;

	if (matches < numfields)
486
		newval = phy_read_mmd(phydev, 2, reg);
487
488
489
490
491
492
493
494
495
496
497
498
499
	else
		newval = 0;

	maxval = (field_sz == 4) ? 0xf : 0x1f;
	for (i = 0; i < numfields; i++)
		if (val[i] != -(i + 1)) {
			mask = 0xffff;
			mask ^= maxval << (field_sz * i);
			newval = (newval & mask) |
				(((val[i] / KSZ9031_PS_TO_REG) & maxval)
					<< (field_sz * i));
		}

500
	return phy_write_mmd(phydev, 2, reg, newval);
501
502
}

503
/* Center KSZ9031RNX FLP timing at 16ms. */
504
505
506
507
static int ksz9031_center_flp_timing(struct phy_device *phydev)
{
	int result;

508
509
	result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
			       0x0006);
510
511
512
	if (result)
		return result;

513
514
	result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
			       0x1A80);
515
516
517
518
519
520
	if (result)
		return result;

	return genphy_restart_aneg(phydev);
}

521
522
523
524
525
/* Enable energy-detect power-down mode */
static int ksz9031_enable_edpd(struct phy_device *phydev)
{
	int reg;

526
	reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
527
528
	if (reg < 0)
		return reg;
529
530
	return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
			     reg | MII_KSZ9031RN_EDPD_ENABLE);
531
532
}

533
534
static int ksz9031_config_init(struct phy_device *phydev)
{
535
	const struct device *dev = &phydev->mdio.dev;
536
537
538
	const struct device_node *of_node = dev->of_node;
	static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
	static const char *rx_data_skews[4] = {
539
540
541
		"rxd0-skew-ps", "rxd1-skew-ps",
		"rxd2-skew-ps", "rxd3-skew-ps"
	};
542
	static const char *tx_data_skews[4] = {
543
544
545
		"txd0-skew-ps", "txd1-skew-ps",
		"txd2-skew-ps", "txd3-skew-ps"
	};
546
	static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
547
	const struct device *dev_walker;
548
549
550
551
552
	int result;

	result = ksz9031_enable_edpd(phydev);
	if (result < 0)
		return result;
553

554
555
556
557
	/* The Micrel driver has a deprecated option to place phy OF
	 * properties in the MAC node. Walk up the tree of devices to
	 * find a device with an OF node.
	 */
558
	dev_walker = &phydev->mdio.dev;
559
560
561
562
	do {
		of_node = dev_walker->of_node;
		dev_walker = dev_walker->parent;
	} while (!of_node && dev_walker);
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579

	if (of_node) {
		ksz9031_of_load_skew_values(phydev, of_node,
				MII_KSZ9031RN_CLK_PAD_SKEW, 5,
				clk_skews, 2);

		ksz9031_of_load_skew_values(phydev, of_node,
				MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
				control_skews, 2);

		ksz9031_of_load_skew_values(phydev, of_node,
				MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
				rx_data_skews, 4);

		ksz9031_of_load_skew_values(phydev, of_node,
				MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
				tx_data_skews, 4);
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606

		/* Silicon Errata Sheet (DS80000691D or DS80000692D):
		 * When the device links in the 1000BASE-T slave mode only,
		 * the optional 125MHz reference output clock (CLK125_NDO)
		 * has wide duty cycle variation.
		 *
		 * The optional CLK125_NDO clock does not meet the RGMII
		 * 45/55 percent (min/max) duty cycle requirement and therefore
		 * cannot be used directly by the MAC side for clocking
		 * applications that have setup/hold time requirements on
		 * rising and falling clock edges.
		 *
		 * Workaround:
		 * Force the phy to be the master to receive a stable clock
		 * which meets the duty cycle requirement.
		 */
		if (of_property_read_bool(of_node, "micrel,force-master")) {
			result = phy_read(phydev, MII_CTRL1000);
			if (result < 0)
				goto err_force_master;

			/* enable master mode, config & prefer master */
			result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
			result = phy_write(phydev, MII_CTRL1000, result);
			if (result < 0)
				goto err_force_master;
		}
607
	}
608
609

	return ksz9031_center_flp_timing(phydev);
610
611
612
613

err_force_master:
	phydev_err(phydev, "failed to force the phy to master mode\n");
	return result;
614
615
}

616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
#define KSZ9131_SKEW_5BIT_MAX	2400
#define KSZ9131_SKEW_4BIT_MAX	800
#define KSZ9131_OFFSET		700
#define KSZ9131_STEP		100

static int ksz9131_of_load_skew_values(struct phy_device *phydev,
				       struct device_node *of_node,
				       u16 reg, size_t field_sz,
				       char *field[], u8 numfields)
{
	int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
		      -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
	int skewval, skewmax = 0;
	int matches = 0;
	u16 maxval;
	u16 newval;
	u16 mask;
	int i;

	/* psec properties in dts should mean x pico seconds */
	if (field_sz == 5)
		skewmax = KSZ9131_SKEW_5BIT_MAX;
	else
		skewmax = KSZ9131_SKEW_4BIT_MAX;

	for (i = 0; i < numfields; i++)
		if (!of_property_read_s32(of_node, field[i], &skewval)) {
			if (skewval < -KSZ9131_OFFSET)
				skewval = -KSZ9131_OFFSET;
			else if (skewval > skewmax)
				skewval = skewmax;

			val[i] = skewval + KSZ9131_OFFSET;
			matches++;
		}

	if (!matches)
		return 0;

	if (matches < numfields)
656
		newval = phy_read_mmd(phydev, 2, reg);
657
658
659
660
661
662
663
664
665
666
667
668
669
	else
		newval = 0;

	maxval = (field_sz == 4) ? 0xf : 0x1f;
	for (i = 0; i < numfields; i++)
		if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
			mask = 0xffff;
			mask ^= maxval << (field_sz * i);
			newval = (newval & mask) |
				(((val[i] / KSZ9131_STEP) & maxval)
					<< (field_sz * i));
		}

670
	return phy_write_mmd(phydev, 2, reg, newval);
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
}

static int ksz9131_config_init(struct phy_device *phydev)
{
	const struct device *dev = &phydev->mdio.dev;
	struct device_node *of_node = dev->of_node;
	char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
	char *rx_data_skews[4] = {
		"rxd0-skew-psec", "rxd1-skew-psec",
		"rxd2-skew-psec", "rxd3-skew-psec"
	};
	char *tx_data_skews[4] = {
		"txd0-skew-psec", "txd1-skew-psec",
		"txd2-skew-psec", "txd3-skew-psec"
	};
	char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
	const struct device *dev_walker;
	int ret;

	dev_walker = &phydev->mdio.dev;
	do {
		of_node = dev_walker->of_node;
		dev_walker = dev_walker->parent;
	} while (!of_node && dev_walker);

	if (!of_node)
		return 0;

	ret = ksz9131_of_load_skew_values(phydev, of_node,
					  MII_KSZ9031RN_CLK_PAD_SKEW, 5,
					  clk_skews, 2);
	if (ret < 0)
		return ret;

	ret = ksz9131_of_load_skew_values(phydev, of_node,
					  MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
					  control_skews, 2);
	if (ret < 0)
		return ret;

	ret = ksz9131_of_load_skew_values(phydev, of_node,
					  MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
					  rx_data_skews, 4);
	if (ret < 0)
		return ret;

	ret = ksz9131_of_load_skew_values(phydev, of_node,
					  MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
					  tx_data_skews, 4);
	if (ret < 0)
		return ret;

	return 0;
}

726
#define KSZ8873MLL_GLOBAL_CONTROL_4	0x06
Johan Hovold's avatar
Johan Hovold committed
727
728
#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX	BIT(6)
#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED	BIT(4)
729
static int ksz8873mll_read_status(struct phy_device *phydev)
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
{
	int regval;

	/* dummy read */
	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);

	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);

	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
		phydev->duplex = DUPLEX_HALF;
	else
		phydev->duplex = DUPLEX_FULL;

	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
		phydev->speed = SPEED_10;
	else
		phydev->speed = SPEED_100;

	phydev->link = 1;
	phydev->pause = phydev->asym_pause = 0;

	return 0;
}

754
755
756
757
758
759
760
761
762
763
764
765
static int ksz9031_get_features(struct phy_device *phydev)
{
	int ret;

	ret = genphy_read_abilities(phydev);
	if (ret < 0)
		return ret;

	/* Silicon Errata Sheet (DS80000691D or DS80000692D):
	 * Whenever the device's Asymmetric Pause capability is set to 1,
	 * link-up may fail after a link-up to link-down transition.
	 *
766
767
	 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
	 *
768
769
770
771
772
773
774
775
776
777
778
779
780
	 * Workaround:
	 * Do not enable the Asymmetric Pause capability bit.
	 */
	linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);

	/* We force setting the Pause capability as the core will force the
	 * Asymmetric Pause capability to 1 otherwise.
	 */
	linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);

	return 0;
}

781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
static int ksz9031_read_status(struct phy_device *phydev)
{
	int err;
	int regval;

	err = genphy_read_status(phydev);
	if (err)
		return err;

	/* Make sure the PHY is not broken. Read idle error count,
	 * and reset the PHY if it is maxed out.
	 */
	regval = phy_read(phydev, MII_STAT1000);
	if ((regval & 0xFF) == 0xFF) {
		phy_init_hw(phydev);
		phydev->link = 0;
797
798
		if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
			phydev->drv->config_intr(phydev);
799
		return genphy_config_aneg(phydev);
800
801
802
803
804
	}

	return 0;
}

805
806
807
808
809
static int ksz8873mll_config_aneg(struct phy_device *phydev)
{
	return 0;
}

810
811
812
813
814
815
816
817
818
819
static int kszphy_get_sset_count(struct phy_device *phydev)
{
	return ARRAY_SIZE(kszphy_hw_stats);
}

static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
820
821
		strlcpy(data + i * ETH_GSTRING_LEN,
			kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
822
823
824
825
826
827
828
	}
}

static u64 kszphy_get_stat(struct phy_device *phydev, int i)
{
	struct kszphy_hw_stat stat = kszphy_hw_stats[i];
	struct kszphy_priv *priv = phydev->priv;
829
830
	int val;
	u64 ret;
831
832
833

	val = phy_read(phydev, stat.reg);
	if (val < 0) {
834
		ret = U64_MAX;
835
836
837
	} else {
		val = val & ((1 << stat.bits) - 1);
		priv->stats[i] += val;
838
		ret = priv->stats[i];
839
840
	}

841
	return ret;
842
843
844
845
846
847
848
849
850
851
852
}

static void kszphy_get_stats(struct phy_device *phydev,
			     struct ethtool_stats *stats, u64 *data)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
		data[i] = kszphy_get_stat(phydev, i);
}

853
static int kszphy_suspend(struct phy_device *phydev)
854
{
855
856
857
858
859
860
	/* Disable PHY Interrupts */
	if (phy_interrupt_is_valid(phydev)) {
		phydev->interrupts = PHY_INTERRUPT_DISABLED;
		if (phydev->drv->config_intr)
			phydev->drv->config_intr(phydev);
	}
861

862
863
	return genphy_suspend(phydev);
}
864

865
866
static int kszphy_resume(struct phy_device *phydev)
{
867
868
	int ret;

869
	genphy_resume(phydev);
870

871
872
873
874
	ret = kszphy_config_reset(phydev);
	if (ret)
		return ret;

875
876
877
878
879
880
	/* Enable PHY Interrupts */
	if (phy_interrupt_is_valid(phydev)) {
		phydev->interrupts = PHY_INTERRUPT_ENABLED;
		if (phydev->drv->config_intr)
			phydev->drv->config_intr(phydev);
	}
881
882
883
884

	return 0;
}

885
886
887
static int kszphy_probe(struct phy_device *phydev)
{
	const struct kszphy_type *type = phydev->drv->driver_data;
888
	const struct device_node *np = phydev->mdio.dev.of_node;
889
	struct kszphy_priv *priv;
890
	struct clk *clk;
891
	int ret;
892

893
	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
894
895
896
897
898
899
900
	if (!priv)
		return -ENOMEM;

	phydev->priv = priv;

	priv->type = type;

901
902
903
904
905
906
907
	if (type->led_mode_reg) {
		ret = of_property_read_u32(np, "micrel,led-mode",
				&priv->led_mode);
		if (ret)
			priv->led_mode = -1;

		if (priv->led_mode > 3) {
908
909
			phydev_err(phydev, "invalid led mode: 0x%02x\n",
				   priv->led_mode);
910
911
912
913
914
915
			priv->led_mode = -1;
		}
	} else {
		priv->led_mode = -1;
	}

916
	clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
917
918
	/* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
	if (!IS_ERR_OR_NULL(clk)) {
919
		unsigned long rate = clk_get_rate(clk);
920
		bool rmii_ref_clk_sel_25_mhz;
921

922
		priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
923
924
		rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
				"micrel,rmii-reference-clock-select-25-mhz");
925

926
		if (rate > 24500000 && rate < 25500000) {
927
			priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
928
		} else if (rate > 49500000 && rate < 50500000) {
929
			priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
930
		} else {
931
932
			phydev_err(phydev, "Clock rate out of range: %ld\n",
				   rate);
933
934
935
936
			return -EINVAL;
		}
	}

937
938
939
940
941
942
943
	/* Support legacy board-file configuration */
	if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
		priv->rmii_ref_clk_sel = true;
		priv->rmii_ref_clk_sel_val = true;
	}

	return 0;
944
945
}

946
947
static struct phy_driver ksphy_driver[] = {
{
Choi, David's avatar
Choi, David committed
948
	.phy_id		= PHY_ID_KS8737,
949
	.phy_id_mask	= MICREL_PHY_ID_MASK,
Choi, David's avatar
Choi, David committed
950
	.name		= "Micrel KS8737",
951
	/* PHY_BASIC_FEATURES */
952
	.driver_data	= &ks8737_type,
Choi, David's avatar
Choi, David committed
953
954
	.config_init	= kszphy_config_init,
	.ack_interrupt	= kszphy_ack_interrupt,
955
	.config_intr	= kszphy_config_intr,
956
957
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
958
959
960
}, {
	.phy_id		= PHY_ID_KSZ8021,
	.phy_id_mask	= 0x00ffffff,
961
	.name		= "Micrel KSZ8021 or KSZ8031",
962
	/* PHY_BASIC_FEATURES */
963
	.driver_data	= &ksz8021_type,
964
	.probe		= kszphy_probe,
965
	.config_init	= kszphy_config_init,
966
967
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
968
969
970
	.get_sset_count = kszphy_get_sset_count,
	.get_strings	= kszphy_get_strings,
	.get_stats	= kszphy_get_stats,
971
972
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
973
974
975
976
}, {
	.phy_id		= PHY_ID_KSZ8031,
	.phy_id_mask	= 0x00ffffff,
	.name		= "Micrel KSZ8031",
977
	/* PHY_BASIC_FEATURES */
978
	.driver_data	= &ksz8021_type,
979
	.probe		= kszphy_probe,
980
	.config_init	= kszphy_config_init,
981
982
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
983
984
985
	.get_sset_count = kszphy_get_sset_count,
	.get_strings	= kszphy_get_strings,
	.get_stats	= kszphy_get_stats,
986
987
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
988
}, {
989
	.phy_id		= PHY_ID_KSZ8041,
990
	.phy_id_mask	= MICREL_PHY_ID_MASK,
991
	.name		= "Micrel KSZ8041",
992
	/* PHY_BASIC_FEATURES */
993
994
	.driver_data	= &ksz8041_type,
	.probe		= kszphy_probe,
995
996
	.config_init	= ksz8041_config_init,
	.config_aneg	= ksz8041_config_aneg,
Choi, David's avatar
Choi, David committed
997
998
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
999
1000
	.get_sset_count = kszphy_get_sset_count,
	.get_strings	= kszphy_get_strings,