mlx5_ifc.h 236 KB
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/*
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 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
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 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
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*/
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#ifndef MLX5_IFC_H
#define MLX5_IFC_H

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#include "mlx5_ifc_fpga.h"

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enum {
	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
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	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
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	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
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};

enum {
	MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
	MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
	MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
	MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
};

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enum {
	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
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	MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
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	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
};

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enum {
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	MLX5_SHARED_RESOURCE_UID = 0xffff,
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};

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enum {
	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
};

enum {
	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
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	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
};

enum {
	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
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	MLX5_OBJ_TYPE_MKEY = 0xff01,
	MLX5_OBJ_TYPE_QP = 0xff02,
	MLX5_OBJ_TYPE_PSV = 0xff03,
	MLX5_OBJ_TYPE_RMP = 0xff04,
	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
	MLX5_OBJ_TYPE_RQ = 0xff06,
	MLX5_OBJ_TYPE_SQ = 0xff07,
	MLX5_OBJ_TYPE_TIR = 0xff08,
	MLX5_OBJ_TYPE_TIS = 0xff09,
	MLX5_OBJ_TYPE_DCT = 0xff0a,
	MLX5_OBJ_TYPE_XRQ = 0xff0b,
	MLX5_OBJ_TYPE_RQT = 0xff0e,
	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
	MLX5_OBJ_TYPE_CQ = 0xff10,
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};

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enum {
	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
	MLX5_CMD_OP_INIT_HCA                      = 0x102,
	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
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	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
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	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
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	MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
	MLX5_CMD_OP_ALLOC_SF                      = 0x113,
	MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
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	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
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	MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
	MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
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	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
	MLX5_CMD_OP_GEN_EQE                       = 0x304,
	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
	MLX5_CMD_OP_CREATE_QP                     = 0x500,
	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
	MLX5_CMD_OP_2ERR_QP                       = 0x507,
	MLX5_CMD_OP_2RST_QP                       = 0x50a,
	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
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	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
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	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
	MLX5_CMD_OP_ARM_RQ                        = 0x703,
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	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
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	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
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	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
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	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
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	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
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	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
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	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
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	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
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	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
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	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
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	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
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	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
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	MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
	MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
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	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
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	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
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	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
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	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
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	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
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	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
	MLX5_CMD_OP_NOP                           = 0x80d,
	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
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	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
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	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
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	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
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	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
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	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
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	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
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	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
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	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
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	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
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	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
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	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
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	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
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	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
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	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
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	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
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	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
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	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
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	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
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	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
	MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
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	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
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	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
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	MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
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	MLX5_CMD_OP_MAX
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};

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/* Valid range for general commands that don't work over an object */
enum {
	MLX5_CMD_OP_GENERAL_START = 0xb00,
	MLX5_CMD_OP_GENERAL_END = 0xd00,
};

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struct mlx5_ifc_flow_table_fields_supported_bits {
	u8         outer_dmac[0x1];
	u8         outer_smac[0x1];
	u8         outer_ether_type[0x1];
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	u8         outer_ip_version[0x1];
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	u8         outer_first_prio[0x1];
	u8         outer_first_cfi[0x1];
	u8         outer_first_vid[0x1];
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	u8         outer_ipv4_ttl[0x1];
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	u8         outer_second_prio[0x1];
	u8         outer_second_cfi[0x1];
	u8         outer_second_vid[0x1];
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	u8         reserved_at_b[0x1];
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	u8         outer_sip[0x1];
	u8         outer_dip[0x1];
	u8         outer_frag[0x1];
	u8         outer_ip_protocol[0x1];
	u8         outer_ip_ecn[0x1];
	u8         outer_ip_dscp[0x1];
	u8         outer_udp_sport[0x1];
	u8         outer_udp_dport[0x1];
	u8         outer_tcp_sport[0x1];
	u8         outer_tcp_dport[0x1];
	u8         outer_tcp_flags[0x1];
	u8         outer_gre_protocol[0x1];
	u8         outer_gre_key[0x1];
	u8         outer_vxlan_vni[0x1];
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	u8         outer_geneve_vni[0x1];
	u8         outer_geneve_oam[0x1];
	u8         outer_geneve_protocol_type[0x1];
	u8         outer_geneve_opt_len[0x1];
	u8         reserved_at_1e[0x1];
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	u8         source_eswitch_port[0x1];

	u8         inner_dmac[0x1];
	u8         inner_smac[0x1];
	u8         inner_ether_type[0x1];
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	u8         inner_ip_version[0x1];
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	u8         inner_first_prio[0x1];
	u8         inner_first_cfi[0x1];
	u8         inner_first_vid[0x1];
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	u8         reserved_at_27[0x1];
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	u8         inner_second_prio[0x1];
	u8         inner_second_cfi[0x1];
	u8         inner_second_vid[0x1];
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	u8         reserved_at_2b[0x1];
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	u8         inner_sip[0x1];
	u8         inner_dip[0x1];
	u8         inner_frag[0x1];
	u8         inner_ip_protocol[0x1];
	u8         inner_ip_ecn[0x1];
	u8         inner_ip_dscp[0x1];
	u8         inner_udp_sport[0x1];
	u8         inner_udp_dport[0x1];
	u8         inner_tcp_sport[0x1];
	u8         inner_tcp_dport[0x1];
	u8         inner_tcp_flags[0x1];
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	u8         reserved_at_37[0x9];
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	u8         geneve_tlv_option_0_data[0x1];
	u8         reserved_at_41[0x4];
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	u8         outer_first_mpls_over_udp[0x4];
	u8         outer_first_mpls_over_gre[0x4];
	u8         inner_first_mpls[0x4];
	u8         outer_first_mpls[0x4];
	u8         reserved_at_55[0x2];
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	u8	   outer_esp_spi[0x1];
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	u8         reserved_at_58[0x2];
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	u8         bth_dst_qp[0x1];
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	u8         reserved_at_5b[0x25];
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};

struct mlx5_ifc_flow_table_prop_layout_bits {
	u8         ft_support[0x1];
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	u8         reserved_at_1[0x1];
	u8         flow_counter[0x1];
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	u8	   flow_modify_en[0x1];
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	u8         modify_root[0x1];
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	u8         identified_miss_table_mode[0x1];
	u8         flow_table_modify[0x1];
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	u8         reformat[0x1];
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	u8         decap[0x1];
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	u8         reserved_at_9[0x1];
	u8         pop_vlan[0x1];
	u8         push_vlan[0x1];
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	u8         reserved_at_c[0x1];
	u8         pop_vlan_2[0x1];
	u8         push_vlan_2[0x1];
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	u8	   reformat_and_vlan_action[0x1];
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	u8	   reserved_at_10[0x1];
	u8         sw_owner[0x1];
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	u8	   reformat_l3_tunnel_to_l2[0x1];
	u8	   reformat_l2_to_l3_tunnel[0x1];
	u8	   reformat_and_modify_action[0x1];
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	u8         reserved_at_15[0x2];
	u8	   table_miss_action_domain[0x1];
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	u8         termination_table[0x1];
	u8         reserved_at_19[0x7];
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	u8         reserved_at_20[0x2];
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	u8         log_max_ft_size[0x6];
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	u8         log_max_modify_header_context[0x8];
	u8         max_modify_header_actions[0x8];
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	u8         max_ft_level[0x8];

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	u8         reserved_at_40[0x20];
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	u8         reserved_at_60[0x18];
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	u8         log_max_ft_num[0x8];

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	u8         reserved_at_80[0x18];
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	u8         log_max_destination[0x8];

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	u8         log_max_flow_counter[0x8];
	u8         reserved_at_a8[0x10];
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	u8         log_max_flow[0x8];

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	u8         reserved_at_c0[0x40];
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	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;

	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
};

struct mlx5_ifc_odp_per_transport_service_cap_bits {
	u8         send[0x1];
	u8         receive[0x1];
	u8         write[0x1];
	u8         read[0x1];
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	u8         atomic[0x1];
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	u8         srq_receive[0x1];
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	u8         reserved_at_6[0x1a];
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};

struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
	u8         smac_47_16[0x20];

	u8         smac_15_0[0x10];
	u8         ethertype[0x10];

	u8         dmac_47_16[0x20];

	u8         dmac_15_0[0x10];
	u8         first_prio[0x3];
	u8         first_cfi[0x1];
	u8         first_vid[0xc];

	u8         ip_protocol[0x8];
	u8         ip_dscp[0x6];
	u8         ip_ecn[0x2];
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	u8         cvlan_tag[0x1];
	u8         svlan_tag[0x1];
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	u8         frag[0x1];
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	u8         ip_version[0x4];
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	u8         tcp_flags[0x9];

	u8         tcp_sport[0x10];
	u8         tcp_dport[0x10];

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	u8         reserved_at_c0[0x18];
	u8         ttl_hoplimit[0x8];
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	u8         udp_sport[0x10];
	u8         udp_dport[0x10];

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	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
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	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
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};

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struct mlx5_ifc_nvgre_key_bits {
	u8 hi[0x18];
	u8 lo[0x8];
};

union mlx5_ifc_gre_key_bits {
	struct mlx5_ifc_nvgre_key_bits nvgre;
	u8 key[0x20];
};

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struct mlx5_ifc_fte_match_set_misc_bits {
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	u8         gre_c_present[0x1];
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	u8         reserved_at_1[0x1];
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	u8         gre_k_present[0x1];
	u8         gre_s_present[0x1];
	u8         source_vhca_port[0x4];
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	u8         source_sqn[0x18];
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	u8         source_eswitch_owner_vhca_id[0x10];
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	u8         source_port[0x10];

	u8         outer_second_prio[0x3];
	u8         outer_second_cfi[0x1];
	u8         outer_second_vid[0xc];
	u8         inner_second_prio[0x3];
	u8         inner_second_cfi[0x1];
	u8         inner_second_vid[0xc];

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	u8         outer_second_cvlan_tag[0x1];
	u8         inner_second_cvlan_tag[0x1];
	u8         outer_second_svlan_tag[0x1];
	u8         inner_second_svlan_tag[0x1];
	u8         reserved_at_64[0xc];
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	u8         gre_protocol[0x10];

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	union mlx5_ifc_gre_key_bits gre_key;
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	u8         vxlan_vni[0x18];
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	u8         reserved_at_b8[0x8];
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	u8         geneve_vni[0x18];
	u8         reserved_at_d8[0x7];
	u8         geneve_oam[0x1];
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	u8         reserved_at_e0[0xc];
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	u8         outer_ipv6_flow_label[0x14];

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	u8         reserved_at_100[0xc];
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	u8         inner_ipv6_flow_label[0x14];

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	u8         reserved_at_120[0xa];
	u8         geneve_opt_len[0x6];
	u8         geneve_protocol_type[0x10];

	u8         reserved_at_140[0x8];
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	u8         bth_dst_qp[0x18];
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	u8	   reserved_at_160[0x20];
	u8	   outer_esp_spi[0x20];
	u8         reserved_at_1a0[0x60];
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};

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struct mlx5_ifc_fte_match_mpls_bits {
	u8         mpls_label[0x14];
	u8         mpls_exp[0x3];
	u8         mpls_s_bos[0x1];
	u8         mpls_ttl[0x8];
};

struct mlx5_ifc_fte_match_set_misc2_bits {
	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;

	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;

	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;

	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;

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	u8         metadata_reg_c_7[0x20];

	u8         metadata_reg_c_6[0x20];

	u8         metadata_reg_c_5[0x20];

	u8         metadata_reg_c_4[0x20];

	u8         metadata_reg_c_3[0x20];

	u8         metadata_reg_c_2[0x20];

	u8         metadata_reg_c_1[0x20];

	u8         metadata_reg_c_0[0x20];
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	u8         metadata_reg_a[0x20];

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	u8         metadata_reg_b[0x20];

	u8         reserved_at_1c0[0x40];
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};

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struct mlx5_ifc_fte_match_set_misc3_bits {
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	u8         inner_tcp_seq_num[0x20];

	u8         outer_tcp_seq_num[0x20];

	u8         inner_tcp_ack_num[0x20];

	u8         outer_tcp_ack_num[0x20];

	u8	   reserved_at_80[0x8];
	u8         outer_vxlan_gpe_vni[0x18];

	u8         outer_vxlan_gpe_next_protocol[0x8];
	u8         outer_vxlan_gpe_flags[0x8];
	u8	   reserved_at_b0[0x10];

	u8	   icmp_header_data[0x20];

	u8	   icmpv6_header_data[0x20];

	u8	   icmp_type[0x8];
	u8	   icmp_code[0x8];
	u8	   icmpv6_type[0x8];
	u8	   icmpv6_code[0x8];

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	u8         geneve_tlv_option_0_data[0x20];
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	u8         reserved_at_140[0xc0];
};

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struct mlx5_ifc_cmd_pas_bits {
	u8         pa_h[0x20];

	u8         pa_l[0x14];
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	u8         reserved_at_34[0xc];
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};

struct mlx5_ifc_uint64_bits {
	u8         hi[0x20];

	u8         lo[0x20];
};

enum {
	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
};

struct mlx5_ifc_ads_bits {
	u8         fl[0x1];
	u8         free_ar[0x1];
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	u8         reserved_at_2[0xe];
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	u8         pkey_index[0x10];

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	u8         reserved_at_20[0x8];
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	u8         grh[0x1];
	u8         mlid[0x7];
	u8         rlid[0x10];

	u8         ack_timeout[0x5];
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	u8         reserved_at_45[0x3];
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	u8         src_addr_index[0x8];
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	u8         reserved_at_50[0x4];
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	u8         stat_rate[0x4];
	u8         hop_limit[0x8];

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	u8         reserved_at_60[0x4];
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	u8         tclass[0x8];
	u8         flow_label[0x14];

	u8         rgid_rip[16][0x8];

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	u8         reserved_at_100[0x4];
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	u8         f_dscp[0x1];
	u8         f_ecn[0x1];
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	u8         reserved_at_106[0x1];
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	u8         f_eth_prio[0x1];
	u8         ecn[0x2];
	u8         dscp[0x6];
	u8         udp_sport[0x10];

	u8         dei_cfi[0x1];
	u8         eth_prio[0x3];
	u8         sl[0x4];
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	u8         vhca_port_num[0x8];
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	u8         rmac_47_32[0x10];

	u8         rmac_31_0[0x20];
};

struct mlx5_ifc_flow_table_nic_cap_bits {
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	u8         nic_rx_multi_path_tirs[0x1];
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	u8         nic_rx_multi_path_tirs_fts[0x1];
	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
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	u8	   reserved_at_3[0x1d];
	u8	   encap_general_header[0x1];
	u8	   reserved_at_21[0xa];
	u8	   log_max_packet_reformat_context[0x5];
	u8	   reserved_at_30[0x6];
	u8	   max_encap_header_size[0xa];
	u8	   reserved_at_40[0x1c0];
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	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;

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	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
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	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;

	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;

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	u8         reserved_at_a00[0x200];
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	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;

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	u8         reserved_at_e00[0x1200];

	u8         sw_steering_nic_rx_action_drop_icm_address[0x40];

	u8         sw_steering_nic_tx_action_drop_icm_address[0x40];

	u8         sw_steering_nic_tx_action_allow_icm_address[0x40];

	u8         reserved_at_20c0[0x5f40];
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};

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enum {
	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
};

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struct mlx5_ifc_flow_table_eswitch_cap_bits {
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	u8      fdb_to_vport_reg_c_id[0x8];
	u8      reserved_at_8[0xf];
	u8      flow_source[0x1];
	u8      reserved_at_18[0x2];
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	u8      multi_fdb_encap[0x1];
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	u8      reserved_at_1b[0x1];
	u8      fdb_multi_path_to_table[0x1];
	u8      reserved_at_1d[0x3];

	u8      reserved_at_20[0x1e0];
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	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;

	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;

	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;

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	u8      reserved_at_800[0x1000];

	u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];

	u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];

	u8      sw_steering_uplink_icm_address_rx[0x40];

	u8      sw_steering_uplink_icm_address_tx[0x40];

	u8      reserved_at_1900[0x6700];
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};

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enum {
	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
	MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
};

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struct mlx5_ifc_e_switch_cap_bits {
	u8         vport_svlan_strip[0x1];
	u8         vport_cvlan_strip[0x1];
	u8         vport_svlan_insert[0x1];
	u8         vport_cvlan_insert_if_not_exist[0x1];
	u8         vport_cvlan_insert_overwrite[0x1];
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	u8         reserved_at_5[0x3];
	u8         esw_uplink_ingress_acl[0x1];
	u8         reserved_at_9[0x10];
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	u8         esw_functions_changed[0x1];
	u8         reserved_at_1a[0x1];
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	u8         ecpf_vport_exists[0x1];
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	u8         counter_eswitch_affinity[0x1];
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	u8         merged_eswitch[0x1];
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	u8         nic_vport_node_guid_modify[0x1];
	u8         nic_vport_port_guid_modify[0x1];
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	u8         vxlan_encap_decap[0x1];
	u8         nvgre_encap_decap[0x1];
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	u8         reserved_at_22[0x1];
	u8         log_max_fdb_encap_uplink[0x5];
	u8         reserved_at_21[0x3];
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	u8         log_max_packet_reformat_context[0x5];
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	u8         reserved_2b[0x6];
	u8         max_encap_header_size[0xa];

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	u8         reserved_at_40[0xb];
	u8         log_max_esw_sf[0x5];
	u8         esw_sf_base_id[0x10];

	u8         reserved_at_60[0x7a0];
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};

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struct mlx5_ifc_qos_cap_bits {
	u8         packet_pacing[0x1];
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	u8         esw_scheduling[0x1];
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	u8         esw_bw_share[0x1];
	u8         esw_rate_limit[0x1];
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	u8         reserved_at_4[0x1];
	u8         packet_pacing_burst_bound[0x1];
	u8         packet_pacing_typical_size[0x1];
	u8         reserved_at_7[0x19];
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	u8         reserved_at_20[0x20];

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	u8         packet_pacing_max_rate[0x20];
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	u8         packet_pacing_min_rate[0x20];
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	u8         reserved_at_80[0x10];
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	u8         packet_pacing_rate_table_size[0x10];
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	u8         esw_element_type[0x10];
	u8         esw_tsar_type[0x10];

	u8         reserved_at_c0[0x10];
	u8         max_qos_para_vport[0x10];

	u8         max_tsar_bw_share[0x20];

	u8         reserved_at_100[0x700];
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};

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struct mlx5_ifc_debug_cap_bits {
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	u8         core_dump_general[0x1];
	u8         core_dump_qp[0x1];
	u8         reserved_at_2[0x1e];
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	u8         reserved_at_20[0x2];
	u8         stall_detect[0x1];
	u8         reserved_at_23[0x1d];

	u8         reserved_at_40[0x7c0];
};

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struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
	u8         csum_cap[0x1];
	u8         vlan_cap[0x1];
	u8         lro_cap[0x1];
	u8         lro_psh_flag[0x1];
	u8         lro_time_stamp[0x1];
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	u8         reserved_at_5[0x2];
	u8         wqe_vlan_insert[0x1];
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	u8         self_lb_en_modifiable[0x1];
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	u8         reserved_at_9[0x2];
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	u8         max_lso_cap[0x5];
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	u8         multi_pkt_send_wqe[0x2];
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	u8	   wqe_inline_mode[0x2];
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	u8         rss_ind_tbl_cap[0x4];
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	u8         reg_umr_sq[0x1];
	u8         scatter_fcs[0x1];
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	u8         enhanced_multi_pkt_send_wqe[0x1];
851
	u8         tunnel_lso_const_out_ip_id[0x1];
852
	u8         reserved_at_1c[0x2];
853
	u8         tunnel_stateless_gre[0x1];
854
855
	u8         tunnel_stateless_vxlan[0x1];

856
857
858
	u8         swp[0x1];
	u8         swp_csum[0x1];
	u8         swp_lso[0x1];
859
	u8         cqe_checksum_full[0x1];
860
861
862
	u8         reserved_at_24[0x5];
	u8         tunnel_stateless_ip_over_ip[0x1];
	u8         reserved_at_2a[0x6];
863
864
	u8         max_vxlan_udp_ports[0x8];
	u8         reserved_at_38[0x6];
865
866
	u8         max_geneve_opt_len[0x1];
	u8         tunnel_stateless_geneve_rx[0x1];
867

868
	u8         reserved_at_40[0x10];
869
870
	u8         lro_min_mss_size[0x10];

871
	u8         reserved_at_60[0x120];
872
873
874

	u8         lro_timer_supported_periods[4][0x20];

875
	u8         reserved_at_200[0x600];
876
877
878
879
};

struct mlx5_ifc_roce_cap_bits {
	u8         roce_apm[0x1];
880
	u8         reserved_at_1[0x1f];
881

882
	u8         reserved_at_20[0x60];
883

884
	u8         reserved_at_80[0xc];
885
	u8         l3_type[0x4];
886
	u8         reserved_at_90[0x8];
887
888
	u8         roce_version[0x8];

889
	u8         reserved_at_a0[0x10];
890
891
892
893
894
	u8         r_roce_dest_udp_port[0x10];

	u8         r_roce_max_src_udp_port[0x10];
	u8         r_roce_min_src_udp_port[0x10];

895
	u8         reserved_at_e0[0x10];
896
897
	u8         roce_address_table_size[0x10];

898
	u8         reserved_at_100[0x700];
899
900
};

901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
struct mlx5_ifc_sync_steering_in_bits {
	u8         opcode[0x10];
	u8         uid[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0xc0];
};

struct mlx5_ifc_sync_steering_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
struct mlx5_ifc_device_mem_cap_bits {
	u8         memic[0x1];
	u8         reserved_at_1[0x1f];

	u8         reserved_at_20[0xb];
	u8         log_min_memic_alloc_size[0x5];
	u8         reserved_at_30[0x8];
	u8	   log_max_memic_addr_alignment[0x8];

	u8         memic_bar_start_addr[0x40];

	u8         memic_bar_size[0x20];

	u8         max_memic_size[0x20];

935
936
937
938
939
940
941
942
943
944
945
946
947
	u8         steering_sw_icm_start_address[0x40];

	u8         reserved_at_100[0x8];
	u8         log_header_modify_sw_icm_size[0x8];
	u8         reserved_at_110[0x2];
	u8         log_sw_icm_alloc_granularity[0x6];
	u8         log_steering_sw_icm_size[0x8];

	u8         reserved_at_120[0x20];

	u8         header_modify_sw_icm_start_address[0x40];

	u8         reserved_at_180[0x680];
948
949
};

950
951
952
953
954
955
struct mlx5_ifc_device_event_cap_bits {
	u8         user_affiliated_events[4][0x40];

	u8         user_unaffiliated_events[4][0x40];
};

956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
enum {
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
};

enum {
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
};

struct mlx5_ifc_atomic_caps_bits {
981
	u8         reserved_at_0[0x40];
982

983
	u8         atomic_req_8B_endianness_mode[0x2];
984
	u8         reserved_at_42[0x4];
985
	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
986

987
	u8         reserved_at_47[0x19];
988

989
	u8         reserved_at_60[0x20];
990

991
	u8         reserved_at_80[0x10];
992
	u8         atomic_operations[0x10];
993

994
	u8         reserved_at_a0[0x10];
995
996
	u8         atomic_size_qp[0x10];

997
	u8         reserved_at_c0[0x10];
998
999
	u8         atomic_size_dc[0x10];

1000
	u8         reserved_at_e0[0x720];