radix_pgtable.c 27.6 KB
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
 * Page table handling routines for radix page table.
 *
 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
 */
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#define pr_fmt(fmt) "radix-mmu: " fmt

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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/sched/mm.h>
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#include <linux/memblock.h>
#include <linux/of_fdt.h>
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#include <linux/mm.h>
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#include <linux/string_helpers.h>
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#include <linux/stop_machine.h>
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#include <asm/pgtable.h>
#include <asm/pgalloc.h>
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#include <asm/mmu_context.h>
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#include <asm/dma.h>
#include <asm/machdep.h>
#include <asm/mmu.h>
#include <asm/firmware.h>
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#include <asm/powernv.h>
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#include <asm/sections.h>
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#include <asm/trace.h>
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#include <asm/uaccess.h>
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#include <asm/ultravisor.h>
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#include <trace/events/thp.h>

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unsigned int mmu_pid_bits;
unsigned int mmu_base_pid;

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static __ref void *early_alloc_pgtable(unsigned long size, int nid,
			unsigned long region_start, unsigned long region_end)
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{
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	phys_addr_t min_addr = MEMBLOCK_LOW_LIMIT;
	phys_addr_t max_addr = MEMBLOCK_ALLOC_ANYWHERE;
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	void *ptr;
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	if (region_start)
		min_addr = region_start;
	if (region_end)
		max_addr = region_end;
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	ptr = memblock_alloc_try_nid(size, size, min_addr, max_addr, nid);

	if (!ptr)
		panic("%s: Failed to allocate %lu bytes align=0x%lx nid=%d from=%pa max_addr=%pa\n",
		      __func__, size, size, nid, &min_addr, &max_addr);

	return ptr;
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}

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static int early_map_kernel_page(unsigned long ea, unsigned long pa,
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			  pgprot_t flags,
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			  unsigned int map_page_size,
			  int nid,
			  unsigned long region_start, unsigned long region_end)
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{
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	unsigned long pfn = pa >> PAGE_SHIFT;
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	pgd_t *pgdp;
	pud_t *pudp;
	pmd_t *pmdp;
	pte_t *ptep;

	pgdp = pgd_offset_k(ea);
	if (pgd_none(*pgdp)) {
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		pudp = early_alloc_pgtable(PUD_TABLE_SIZE, nid,
						region_start, region_end);
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		pgd_populate(&init_mm, pgdp, pudp);
	}
	pudp = pud_offset(pgdp, ea);
	if (map_page_size == PUD_SIZE) {
		ptep = (pte_t *)pudp;
		goto set_the_pte;
	}
	if (pud_none(*pudp)) {
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		pmdp = early_alloc_pgtable(PMD_TABLE_SIZE, nid,
						region_start, region_end);
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		pud_populate(&init_mm, pudp, pmdp);
	}
	pmdp = pmd_offset(pudp, ea);
	if (map_page_size == PMD_SIZE) {
		ptep = pmdp_ptep(pmdp);
		goto set_the_pte;
	}
	if (!pmd_present(*pmdp)) {
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		ptep = early_alloc_pgtable(PAGE_SIZE, nid,
						region_start, region_end);
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		pmd_populate_kernel(&init_mm, pmdp, ptep);
	}
	ptep = pte_offset_kernel(pmdp, ea);

set_the_pte:
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	set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
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	smp_wmb();
	return 0;
}

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/*
 * nid, region_start, and region_end are hints to try to place the page
 * table memory in the same node or region.
 */
static int __map_kernel_page(unsigned long ea, unsigned long pa,
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			  pgprot_t flags,
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			  unsigned int map_page_size,
			  int nid,
			  unsigned long region_start, unsigned long region_end)
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{
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	unsigned long pfn = pa >> PAGE_SHIFT;
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	pgd_t *pgdp;
	pud_t *pudp;
	pmd_t *pmdp;
	pte_t *ptep;
	/*
	 * Make sure task size is correct as per the max adddr
	 */
	BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
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#ifdef CONFIG_PPC_64K_PAGES
	BUILD_BUG_ON(RADIX_KERN_MAP_SIZE != (1UL << MAX_EA_BITS_PER_CONTEXT));
#endif

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	if (unlikely(!slab_is_available()))
		return early_map_kernel_page(ea, pa, flags, map_page_size,
						nid, region_start, region_end);
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	/*
	 * Should make page table allocation functions be able to take a
	 * node, so we can place kernel page tables on the right nodes after
	 * boot.
	 */
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	pgdp = pgd_offset_k(ea);
	pudp = pud_alloc(&init_mm, pgdp, ea);
	if (!pudp)
		return -ENOMEM;
	if (map_page_size == PUD_SIZE) {
		ptep = (pte_t *)pudp;
		goto set_the_pte;
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	}
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	pmdp = pmd_alloc(&init_mm, pudp, ea);
	if (!pmdp)
		return -ENOMEM;
	if (map_page_size == PMD_SIZE) {
		ptep = pmdp_ptep(pmdp);
		goto set_the_pte;
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	}
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	ptep = pte_alloc_kernel(pmdp, ea);
	if (!ptep)
		return -ENOMEM;
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set_the_pte:
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	set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
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	smp_wmb();
	return 0;
}

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int radix__map_kernel_page(unsigned long ea, unsigned long pa,
			  pgprot_t flags,
			  unsigned int map_page_size)
{
	return __map_kernel_page(ea, pa, flags, map_page_size, -1, 0, 0);
}

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#ifdef CONFIG_STRICT_KERNEL_RWX
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void radix__change_memory_range(unsigned long start, unsigned long end,
				unsigned long clear)
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{
	unsigned long idx;
	pgd_t *pgdp;
	pud_t *pudp;
	pmd_t *pmdp;
	pte_t *ptep;

	start = ALIGN_DOWN(start, PAGE_SIZE);
	end = PAGE_ALIGN(end); // aligns up

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	pr_debug("Changing flags on range %lx-%lx removing 0x%lx\n",
		 start, end, clear);
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	for (idx = start; idx < end; idx += PAGE_SIZE) {
		pgdp = pgd_offset_k(idx);
		pudp = pud_alloc(&init_mm, pgdp, idx);
		if (!pudp)
			continue;
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		if (pud_is_leaf(*pudp)) {
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			ptep = (pte_t *)pudp;
			goto update_the_pte;
		}
		pmdp = pmd_alloc(&init_mm, pudp, idx);
		if (!pmdp)
			continue;
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		if (pmd_is_leaf(*pmdp)) {
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			ptep = pmdp_ptep(pmdp);
			goto update_the_pte;
		}
		ptep = pte_alloc_kernel(pmdp, idx);
		if (!ptep)
			continue;
update_the_pte:
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		radix__pte_update(&init_mm, idx, ptep, clear, 0, 0);
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	}

	radix__flush_tlb_kernel_range(start, end);
}
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void radix__mark_rodata_ro(void)
{
	unsigned long start, end;

	start = (unsigned long)_stext;
	end = (unsigned long)__init_begin;

	radix__change_memory_range(start, end, _PAGE_WRITE);
}
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void radix__mark_initmem_nx(void)
{
	unsigned long start = (unsigned long)__init_begin;
	unsigned long end = (unsigned long)__init_end;

	radix__change_memory_range(start, end, _PAGE_EXEC);
}
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#endif /* CONFIG_STRICT_KERNEL_RWX */

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static inline void __meminit
print_mapping(unsigned long start, unsigned long end, unsigned long size, bool exec)
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{
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	char buf[10];

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	if (end <= start)
		return;

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	string_get_size(size, 1, STRING_UNITS_2, buf, sizeof(buf));

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	pr_info("Mapped 0x%016lx-0x%016lx with %s pages%s\n", start, end, buf,
		exec ? " (exec)" : "");
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}

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static unsigned long next_boundary(unsigned long addr, unsigned long end)
{
#ifdef CONFIG_STRICT_KERNEL_RWX
	if (addr < __pa_symbol(__init_begin))
		return __pa_symbol(__init_begin);
#endif
	return end;
}

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static int __meminit create_physical_mapping(unsigned long start,
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					     unsigned long end,
					     int nid)
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{
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	unsigned long vaddr, addr, mapping_size = 0;
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	bool prev_exec, exec = false;
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	pgprot_t prot;
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	int psize;
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	start = _ALIGN_UP(start, PAGE_SIZE);
	for (addr = start; addr < end; addr += mapping_size) {
		unsigned long gap, previous_size;
		int rc;

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		gap = next_boundary(addr, end) - addr;
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		previous_size = mapping_size;
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		prev_exec = exec;
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		if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE &&
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		    mmu_psize_defs[MMU_PAGE_1G].shift) {
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			mapping_size = PUD_SIZE;
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			psize = MMU_PAGE_1G;
		} else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE &&
			   mmu_psize_defs[MMU_PAGE_2M].shift) {
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			mapping_size = PMD_SIZE;
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			psize = MMU_PAGE_2M;
		} else {
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			mapping_size = PAGE_SIZE;
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			psize = mmu_virtual_psize;
		}
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		vaddr = (unsigned long)__va(addr);

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		if (overlaps_kernel_text(vaddr, vaddr + mapping_size) ||
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		    overlaps_interrupt_vector_text(vaddr, vaddr + mapping_size)) {
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			prot = PAGE_KERNEL_X;
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			exec = true;
		} else {
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			prot = PAGE_KERNEL;
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			exec = false;
		}

		if (mapping_size != previous_size || exec != prev_exec) {
			print_mapping(start, addr, previous_size, prev_exec);
			start = addr;
		}
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		rc = __map_kernel_page(vaddr, addr, prot, mapping_size, nid, start, end);
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		if (rc)
			return rc;
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		update_page_count(psize, 1);
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	}

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	print_mapping(start, addr, mapping_size, exec);
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	return 0;
}

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static void __init radix_init_pgtable(void)
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{
	unsigned long rts_field;
	struct memblock_region *reg;

	/* We don't support slb for radix */
	mmu_slb_size = 0;
	/*
	 * Create the linear mapping, using standard page size for now
	 */
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	for_each_memblock(memory, reg) {
		/*
		 * The memblock allocator  is up at this point, so the
		 * page tables will be allocated within the range. No
		 * need or a node (which we don't have yet).
		 */
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		if ((reg->base + reg->size) >= RADIX_VMALLOC_START) {
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			pr_warn("Outside the supported range\n");
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			continue;
		}

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		WARN_ON(create_physical_mapping(reg->base,
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						reg->base + reg->size,
						-1));
	}
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	/* Find out how many PID bits are supported */
	if (cpu_has_feature(CPU_FTR_HVMODE)) {
		if (!mmu_pid_bits)
			mmu_pid_bits = 20;
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
		/*
		 * When KVM is possible, we only use the top half of the
		 * PID space to avoid collisions between host and guest PIDs
		 * which can cause problems due to prefetch when exiting the
		 * guest with AIL=3
		 */
		mmu_base_pid = 1 << (mmu_pid_bits - 1);
#else
		mmu_base_pid = 1;
#endif
	} else {
		/* The guest uses the bottom half of the PID space */
		if (!mmu_pid_bits)
			mmu_pid_bits = 19;
		mmu_base_pid = 1;
	}

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	/*
	 * Allocate Partition table and process table for the
	 * host.
	 */
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	BUG_ON(PRTB_SIZE_SHIFT > 36);
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	process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT, -1, 0, 0);
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	/*
	 * Fill in the process table.
	 */
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	rts_field = radix__get_tree_size();
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	process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
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	/*
	 * The init_mm context is given the first available (non-zero) PID,
	 * which is the "guard PID" and contains no page table. PIDR should
	 * never be set to zero because that duplicates the kernel address
	 * space at the 0x0... offset (quadrant 0)!
	 *
	 * An arbitrary PID that may later be allocated by the PID allocator
	 * for userspace processes must not be used either, because that
	 * would cause stale user mappings for that PID on CPUs outside of
	 * the TLB invalidation scheme (because it won't be in mm_cpumask).
	 *
	 * So permanently carve out one PID for the purpose of a guard PID.
	 */
	init_mm.context.id = mmu_base_pid;
	mmu_base_pid++;
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}

static void __init radix_init_partition_table(void)
{
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	unsigned long rts_field, dw0, dw1;
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	mmu_partition_table_init();
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	rts_field = radix__get_tree_size();
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	dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR;
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	dw1 = __pa(process_tb) | (PRTB_SIZE_SHIFT - 12) | PATB_GR;
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	mmu_partition_table_set_entry(0, dw0, dw1, false);
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	pr_info("Initializing Radix MMU\n");
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}

static int __init get_idx_from_shift(unsigned int shift)
{
	int idx = -1;

	switch (shift) {
	case 0xc:
		idx = MMU_PAGE_4K;
		break;
	case 0x10:
		idx = MMU_PAGE_64K;
		break;
	case 0x15:
		idx = MMU_PAGE_2M;
		break;
	case 0x1e:
		idx = MMU_PAGE_1G;
		break;
	}
	return idx;
}

static int __init radix_dt_scan_page_sizes(unsigned long node,
					   const char *uname, int depth,
					   void *data)
{
	int size = 0;
	int shift, idx;
	unsigned int ap;
	const __be32 *prop;
	const char *type = of_get_flat_dt_prop(node, "device_type", NULL);

	/* We are scanning "cpu" nodes only */
	if (type == NULL || strcmp(type, "cpu") != 0)
		return 0;

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	/* Find MMU PID size */
	prop = of_get_flat_dt_prop(node, "ibm,mmu-pid-bits", &size);
	if (prop && size == 4)
		mmu_pid_bits = be32_to_cpup(prop);

	/* Grab page size encodings */
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	prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
	if (!prop)
		return 0;

	pr_info("Page sizes from device-tree:\n");
	for (; size >= 4; size -= 4, ++prop) {

		struct mmu_psize_def *def;

		/* top 3 bit is AP encoding */
		shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
		ap = be32_to_cpu(prop[0]) >> 29;
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		pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
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		idx = get_idx_from_shift(shift);
		if (idx < 0)
			continue;

		def = &mmu_psize_defs[idx];
		def->shift = shift;
		def->ap  = ap;
	}

	/* needed ? */
	cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
	return 1;
}

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void __init radix__early_init_devtree(void)
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{
	int rc;

	/*
	 * Try to find the available page sizes in the device-tree
	 */
	rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
	if (rc != 0)  /* Found */
		goto found;
	/*
	 * let's assume we have page 4k and 64k support
	 */
	mmu_psize_defs[MMU_PAGE_4K].shift = 12;
	mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;

	mmu_psize_defs[MMU_PAGE_64K].shift = 16;
	mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
found:
	return;
}

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static void radix_init_amor(void)
{
	/*
	* In HV mode, we init AMOR (Authority Mask Override Register) so that
	* the hypervisor and guest can setup IAMR (Instruction Authority Mask
	* Register), enable key 0 and set it to 1.
	*
	* AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
	*/
	mtspr(SPRN_AMOR, (3ul << 62));
}

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#ifdef CONFIG_PPC_KUEP
void setup_kuep(bool disabled)
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{
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	if (disabled || !early_radix_enabled())
		return;

	if (smp_processor_id() == boot_cpuid)
		pr_info("Activating Kernel Userspace Execution Prevention\n");

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	/*
	 * Radix always uses key0 of the IAMR to determine if an access is
	 * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction
	 * fetch.
	 */
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	mtspr(SPRN_IAMR, (1ul << 62));
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}
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#endif
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#ifdef CONFIG_PPC_KUAP
void setup_kuap(bool disabled)
{
	if (disabled || !early_radix_enabled())
		return;

	if (smp_processor_id() == boot_cpuid) {
		pr_info("Activating Kernel Userspace Access Prevention\n");
		cur_cpu_spec->mmu_features |= MMU_FTR_RADIX_KUAP;
	}

	/* Make sure userspace can't change the AMR */
	mtspr(SPRN_UAMOR, 0);
	mtspr(SPRN_AMR, AMR_KUAP_BLOCKED);
	isync();
}
#endif

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void __init radix__early_init_mmu(void)
{
	unsigned long lpcr;

#ifdef CONFIG_PPC_64K_PAGES
	/* PAGE_SIZE mappings */
	mmu_virtual_psize = MMU_PAGE_64K;
#else
	mmu_virtual_psize = MMU_PAGE_4K;
#endif

#ifdef CONFIG_SPARSEMEM_VMEMMAP
	/* vmemmap mapping */
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	if (mmu_psize_defs[MMU_PAGE_2M].shift) {
		/*
		 * map vmemmap using 2M if available
		 */
		mmu_vmemmap_psize = MMU_PAGE_2M;
	} else
		mmu_vmemmap_psize = mmu_virtual_psize;
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#endif
	/*
	 * initialize page table size
	 */
	__pte_index_size = RADIX_PTE_INDEX_SIZE;
	__pmd_index_size = RADIX_PMD_INDEX_SIZE;
	__pud_index_size = RADIX_PUD_INDEX_SIZE;
	__pgd_index_size = RADIX_PGD_INDEX_SIZE;
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	__pud_cache_index = RADIX_PUD_INDEX_SIZE;
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	__pte_table_size = RADIX_PTE_TABLE_SIZE;
	__pmd_table_size = RADIX_PMD_TABLE_SIZE;
	__pud_table_size = RADIX_PUD_TABLE_SIZE;
	__pgd_table_size = RADIX_PGD_TABLE_SIZE;

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	__pmd_val_bits = RADIX_PMD_VAL_BITS;
	__pud_val_bits = RADIX_PUD_VAL_BITS;
	__pgd_val_bits = RADIX_PGD_VAL_BITS;
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	__kernel_virt_start = RADIX_KERN_VIRT_START;
	__vmalloc_start = RADIX_VMALLOC_START;
	__vmalloc_end = RADIX_VMALLOC_END;
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	__kernel_io_start = RADIX_KERN_IO_START;
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	__kernel_io_end = RADIX_KERN_IO_END;
584
	vmemmap = (struct page *)RADIX_VMEMMAP_START;
585
	ioremap_bot = IOREMAP_BASE;
586
587
588
589

#ifdef CONFIG_PCI
	pci_io_base = ISA_IO_BASE;
#endif
590
591
	__pte_frag_nr = RADIX_PTE_FRAG_NR;
	__pte_frag_size_shift = RADIX_PTE_FRAG_SIZE_SHIFT;
592
593
	__pmd_frag_nr = RADIX_PMD_FRAG_NR;
	__pmd_frag_size_shift = RADIX_PMD_FRAG_SIZE_SHIFT;
594

595
596
	radix_init_pgtable();

597
598
	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
		lpcr = mfspr(SPRN_LPCR);
599
		mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
600
		radix_init_partition_table();
601
		radix_init_amor();
602
603
	} else {
		radix_init_pseries();
604
	}
605

606
607
	memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);

608
609
	/* Switch to the guard PID before turning on MMU */
	radix__switch_mmu_context(NULL, &init_mm);
610
	tlbiel_all();
611
612
613
614
615
616
}

void radix__early_init_mmu_secondary(void)
{
	unsigned long lpcr;
	/*
617
	 * update partition table control register and UPRT
618
	 */
619
620
	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
		lpcr = mfspr(SPRN_LPCR);
621
		mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
622

623
624
625
		set_ptcr_when_no_uv(__pa(partition_tb) |
				    (PATB_SIZE_SHIFT - 12));

626
		radix_init_amor();
627
	}
628

629
	radix__switch_mmu_context(NULL, &init_mm);
630
	tlbiel_all();
631
632
}

633
634
635
636
637
638
639
void radix__mmu_cleanup_all(void)
{
	unsigned long lpcr;

	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
		lpcr = mfspr(SPRN_LPCR);
		mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
640
		set_ptcr_when_no_uv(0);
641
		powernv_set_nmmu_ptcr(0);
642
643
644
645
		radix__flush_tlb_all();
	}
}

646
647
648
void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
				phys_addr_t first_memblock_size)
{
649
650
	/*
	 * We don't currently support the first MEMBLOCK not mapping 0
651
652
653
	 * physical on those processors
	 */
	BUG_ON(first_memblock_base != 0);
654

655
656
657
658
	/*
	 * Radix mode is not limited by RMA / VRMA addressing.
	 */
	ppc64_rma_size = ULONG_MAX;
659
}
660

661
#ifdef CONFIG_MEMORY_HOTPLUG
662
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664
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691
static void free_pte_table(pte_t *pte_start, pmd_t *pmd)
{
	pte_t *pte;
	int i;

	for (i = 0; i < PTRS_PER_PTE; i++) {
		pte = pte_start + i;
		if (!pte_none(*pte))
			return;
	}

	pte_free_kernel(&init_mm, pte_start);
	pmd_clear(pmd);
}

static void free_pmd_table(pmd_t *pmd_start, pud_t *pud)
{
	pmd_t *pmd;
	int i;

	for (i = 0; i < PTRS_PER_PMD; i++) {
		pmd = pmd_start + i;
		if (!pmd_none(*pmd))
			return;
	}

	pmd_free(&init_mm, pmd_start);
	pud_clear(pud);
}

692
693
694
695
696
697
698
699
struct change_mapping_params {
	pte_t *pte;
	unsigned long start;
	unsigned long end;
	unsigned long aligned_start;
	unsigned long aligned_end;
};

700
static int __meminit stop_machine_change_mapping(void *data)
701
702
703
704
705
706
707
708
709
{
	struct change_mapping_params *params =
			(struct change_mapping_params *)data;

	if (!data)
		return -1;

	spin_unlock(&init_mm.page_table_lock);
	pte_clear(&init_mm, params->aligned_start, params->pte);
710
711
	create_physical_mapping(__pa(params->aligned_start), __pa(params->start), -1);
	create_physical_mapping(__pa(params->end), __pa(params->aligned_end), -1);
712
713
714
715
	spin_lock(&init_mm.page_table_lock);
	return 0;
}

716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
static void remove_pte_table(pte_t *pte_start, unsigned long addr,
			     unsigned long end)
{
	unsigned long next;
	pte_t *pte;

	pte = pte_start + pte_index(addr);
	for (; addr < end; addr = next, pte++) {
		next = (addr + PAGE_SIZE) & PAGE_MASK;
		if (next > end)
			next = end;

		if (!pte_present(*pte))
			continue;

731
732
733
734
735
736
737
738
739
		if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) {
			/*
			 * The vmemmap_free() and remove_section_mapping()
			 * codepaths call us with aligned addresses.
			 */
			WARN_ONCE(1, "%s: unaligned range\n", __func__);
			continue;
		}

740
741
742
743
		pte_clear(&init_mm, addr, pte);
	}
}

744
745
746
/*
 * clear the pte and potentially split the mapping helper
 */
747
static void __meminit split_kernel_mapping(unsigned long addr, unsigned long end,
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
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774
775
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780
781
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783
784
785
786
787
788
789
				unsigned long size, pte_t *pte)
{
	unsigned long mask = ~(size - 1);
	unsigned long aligned_start = addr & mask;
	unsigned long aligned_end = addr + size;
	struct change_mapping_params params;
	bool split_region = false;

	if ((end - addr) < size) {
		/*
		 * We're going to clear the PTE, but not flushed
		 * the mapping, time to remap and flush. The
		 * effects if visible outside the processor or
		 * if we are running in code close to the
		 * mapping we cleared, we are in trouble.
		 */
		if (overlaps_kernel_text(aligned_start, addr) ||
			overlaps_kernel_text(end, aligned_end)) {
			/*
			 * Hack, just return, don't pte_clear
			 */
			WARN_ONCE(1, "Linear mapping %lx->%lx overlaps kernel "
				  "text, not splitting\n", addr, end);
			return;
		}
		split_region = true;
	}

	if (split_region) {
		params.pte = pte;
		params.start = addr;
		params.end = end;
		params.aligned_start = addr & ~(size - 1);
		params.aligned_end = min_t(unsigned long, aligned_end,
				(unsigned long)__va(memblock_end_of_DRAM()));
		stop_machine(stop_machine_change_mapping, &params, NULL);
		return;
	}

	pte_clear(&init_mm, addr, pte);
}

790
791
792
793
794
795
796
797
798
799
800
801
802
803
static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr,
			     unsigned long end)
{
	unsigned long next;
	pte_t *pte_base;
	pmd_t *pmd;

	pmd = pmd_start + pmd_index(addr);
	for (; addr < end; addr = next, pmd++) {
		next = pmd_addr_end(addr, end);

		if (!pmd_present(*pmd))
			continue;

804
		if (pmd_is_leaf(*pmd)) {
805
			split_kernel_mapping(addr, end, PMD_SIZE, (pte_t *)pmd);
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
			continue;
		}

		pte_base = (pte_t *)pmd_page_vaddr(*pmd);
		remove_pte_table(pte_base, addr, next);
		free_pte_table(pte_base, pmd);
	}
}

static void remove_pud_table(pud_t *pud_start, unsigned long addr,
			     unsigned long end)
{
	unsigned long next;
	pmd_t *pmd_base;
	pud_t *pud;

	pud = pud_start + pud_index(addr);
	for (; addr < end; addr = next, pud++) {
		next = pud_addr_end(addr, end);

		if (!pud_present(*pud))
			continue;

829
		if (pud_is_leaf(*pud)) {
830
			split_kernel_mapping(addr, end, PUD_SIZE, (pte_t *)pud);
831
832
833
834
835
836
837
838
839
			continue;
		}

		pmd_base = (pmd_t *)pud_page_vaddr(*pud);
		remove_pmd_table(pmd_base, addr, next);
		free_pmd_table(pmd_base, pud);
	}
}

840
static void __meminit remove_pagetable(unsigned long start, unsigned long end)
841
842
843
844
845
846
847
848
849
850
851
852
853
854
{
	unsigned long addr, next;
	pud_t *pud_base;
	pgd_t *pgd;

	spin_lock(&init_mm.page_table_lock);

	for (addr = start; addr < end; addr = next) {
		next = pgd_addr_end(addr, end);

		pgd = pgd_offset_k(addr);
		if (!pgd_present(*pgd))
			continue;

855
		if (pgd_is_leaf(*pgd)) {
856
			split_kernel_mapping(addr, end, PGDIR_SIZE, (pte_t *)pgd);
857
858
859
860
861
862
863
864
865
866
867
			continue;
		}

		pud_base = (pud_t *)pgd_page_vaddr(*pgd);
		remove_pud_table(pud_base, addr, next);
	}

	spin_unlock(&init_mm.page_table_lock);
	radix__flush_tlb_kernel_range(start, end);
}

868
int __meminit radix__create_section_mapping(unsigned long start, unsigned long end, int nid)
869
{
870
	if (end >= RADIX_VMALLOC_START) {
871
		pr_warn("Outside the supported range\n");
872
873
874
		return -1;
	}

875
	return create_physical_mapping(__pa(start), __pa(end), nid);
876
}
877

878
int __meminit radix__remove_section_mapping(unsigned long start, unsigned long end)
879
880
881
882
{
	remove_pagetable(start, end);
	return 0;
}
883
884
#endif /* CONFIG_MEMORY_HOTPLUG */

885
#ifdef CONFIG_SPARSEMEM_VMEMMAP
886
887
888
889
890
891
892
static int __map_kernel_page_nid(unsigned long ea, unsigned long pa,
				 pgprot_t flags, unsigned int map_page_size,
				 int nid)
{
	return __map_kernel_page(ea, pa, flags, map_page_size, nid, 0, 0);
}

893
894
895
896
897
898
int __meminit radix__vmemmap_create_mapping(unsigned long start,
				      unsigned long page_size,
				      unsigned long phys)
{
	/* Create a PTE encoding */
	unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;
899
900
901
	int nid = early_pfn_to_nid(phys >> PAGE_SHIFT);
	int ret;

902
	if ((start + page_size) >= RADIX_VMEMMAP_END) {
903
		pr_warn("Outside the supported range\n");
904
905
906
		return -1;
	}

907
908
	ret = __map_kernel_page_nid(start, phys, __pgprot(flags), page_size, nid);
	BUG_ON(ret);
909
910
911
912
913

	return 0;
}

#ifdef CONFIG_MEMORY_HOTPLUG
914
void __meminit radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
915
{
916
	remove_pagetable(start, start + page_size);
917
918
919
}
#endif
#endif
920
921
922
923
924
925
926
927
928
929

#ifdef CONFIG_TRANSPARENT_HUGEPAGE

unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
				  pmd_t *pmdp, unsigned long clr,
				  unsigned long set)
{
	unsigned long old;

#ifdef CONFIG_DEBUG_VM
930
	WARN_ON(!radix__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp));
931
	assert_spin_locked(pmd_lockptr(mm, pmdp));
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
#endif

	old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
	trace_hugepage_update(addr, old, clr, set);

	return old;
}

pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
			pmd_t *pmdp)

{
	pmd_t pmd;

	VM_BUG_ON(address & ~HPAGE_PMD_MASK);
	VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
948
	VM_BUG_ON(pmd_devmap(*pmdp));
949
950
951
952
953
	/*
	 * khugepaged calls this for normal pmd
	 */
	pmd = *pmdp;
	pmd_clear(pmdp);
954

955
	/*FIXME!!  Verify whether we need this kick below */
956
	serialize_against_pte_lookup(vma->vm_mm);
957
958
959

	radix__flush_tlb_collapsed_pmd(vma->vm_mm, address);

960
961
962
963
964
965
966
967
968
969
970
971
	return pmd;
}

/*
 * For us pgtable_t is pte_t *. Inorder to save the deposisted
 * page table, we consider the allocated page table as a list
 * head. On withdraw we need to make sure we zero out the used
 * list_head memory area.
 */
void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
				 pgtable_t pgtable)
{
972
	struct list_head *lh = (struct list_head *) pgtable;
973

974
	assert_spin_locked(pmd_lockptr(mm, pmdp));
975

976
977
978
979
980
981
	/* FIFO */
	if (!pmd_huge_pte(mm, pmdp))
		INIT_LIST_HEAD(lh);
	else
		list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
	pmd_huge_pte(mm, pmdp) = pgtable;
982
983
984
985
}

pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
{
986
987
988
	pte_t *ptep;
	pgtable_t pgtable;
	struct list_head *lh;
989

990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
	assert_spin_locked(pmd_lockptr(mm, pmdp));

	/* FIFO */
	pgtable = pmd_huge_pte(mm, pmdp);
	lh = (struct list_head *) pgtable;
	if (list_empty(lh))
		pmd_huge_pte(mm, pmdp) = NULL;
	else {
		pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
		list_del(lh);
	}
	ptep = (pte_t *) pgtable;
	*ptep = __pte(0);
	ptep++;
	*ptep = __pte(0);
	return pgtable;
}
1007
1008

pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
1009
				     unsigned long addr, pmd_t *pmdp)
1010
1011
1012
1013
1014
1015
1016
{
	pmd_t old_pmd;
	unsigned long old;

	old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
	old_pmd = __pmd(old);
	/*
1017
	 * Serialize against find_current_mm_pte which does lock-less
1018
1019
1020
1021
1022
1023
	 * lookup in page tables with local interrupts disabled. For huge pages
	 * it casts pmd_t to pte_t. Since format of pte_t is different from
	 * pmd_t we want to prevent transit from pmd pointing to page table
	 * to pmd pointing to huge page (and back) while interrupts are disabled.
	 * We clear pmd to possibly replace it with page table pointer in
	 * different code paths. So make sure we wait for the parallel
1024
	 * find_current_mm_pte to finish.
1025
	 */
1026
	serialize_against_pte_lookup(mm);
1027
1028
1029
1030
	return old_pmd;
}

#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1031

1032
1033
void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep,
				  pte_t entry, unsigned long address, int psize)
1034
{
1035
	struct mm_struct *mm = vma->vm_mm;
1036
1037
	unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED |
					      _PAGE_RW | _PAGE_EXEC);
1038
1039

	unsigned long change = pte_val(entry) ^ pte_val(*ptep);
1040
1041
1042
1043
	/*
	 * To avoid NMMU hang while relaxing access, we need mark
	 * the pte invalid in between.
	 */
1044
	if ((change & _PAGE_RW) && atomic_read(&mm->context.copros) > 0) {
1045
1046
		unsigned long old_pte, new_pte;

1047
		old_pte = __radix_pte_update(ptep, _PAGE_PRESENT, _PAGE_INVALID);
1048
1049
1050
1051
		/*
		 * new value of pte
		 */
		new_pte = old_pte | set;
1052
		radix__flush_tlb_page_psize(mm, address, psize);
1053
		__radix_pte_update(ptep, _PAGE_INVALID, new_pte);
1054
	} else {
1055
		__radix_pte_update(ptep, 0, set);
1056
1057
1058
1059
1060
1061
		/*
		 * Book3S does not require a TLB flush when relaxing access
		 * restrictions when the address space is not attached to a
		 * NMMU, because the core MMU will reload the pte after taking
		 * an access fault, which is defined by the architectue.
		 */
1062
	}
1063
	/* See ptesync comment in radix__set_pte_at */
1064
}
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082

void radix__ptep_modify_prot_commit(struct vm_area_struct *vma,
				    unsigned long addr, pte_t *ptep,
				    pte_t old_pte, pte_t pte)
{
	struct mm_struct *mm = vma->vm_mm;

	/*
	 * To avoid NMMU hang while relaxing access we need to flush the tlb before
	 * we set the new value. We need to do this only for radix, because hash
	 * translation does flush when updating the linux pte.
	 */
	if (is_pte_rw_upgrade(pte_val(old_pte), pte_val(pte)) &&
	    (atomic_read(&mm->context.copros) > 0))
		radix__flush_tlb_page(vma, addr);

	set_pte_at(mm, addr, ptep, pte);
}
1083

1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
int __init arch_ioremap_pud_supported(void)
{
	/* HPT does not cope with large pages in the vmalloc area */
	return radix_enabled();
}

int __init arch_ioremap_pmd_supported(void)
{
	return radix_enabled();
}

int p4d_free_pud_page(p4d_t *p4d, unsigned long addr)
{
	return 0;
}

int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
{
	pte_t *ptep = (pte_t *)pud;
	pte_t new_pud = pfn_pte(__phys_to_pfn(addr), prot);

	if (!radix_enabled())
		return 0;

	set_pte_at(&init_mm, 0 /* radix unused */, ptep, new_pud);

	return 1;
}

int pud_clear_huge(pud_t *pud)
{
	if (pud_huge(*pud)) {
		pud_clear(pud);
		return 1;
	}

	return 0;
}

int pud_free_pmd_page(pud_t *pud, unsigned long addr)
{
	pmd_t *pmd;
	int i;

	pmd = (pmd_t *)pud_page_vaddr(*pud);
	pud_clear(pud);

	flush_tlb_kernel_range(addr, addr + PUD_SIZE);

	for (i = 0; i < PTRS_PER_PMD; i++) {
		if (!pmd_none(pmd[i])) {
			pte_t *pte;
			pte = (pte_t *)pmd_page_vaddr(pmd[i]);

			pte_free_kernel(&init_mm, pte);
		}
	}

	pmd_free(&init_mm, pmd);

	return 1;
}

int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
{
	pte_t *ptep = (pte_t *)pmd;
	pte_t new_pmd = pfn_pte(__phys_to_pfn(addr), prot);

	if (!radix_enabled())
		return 0;

	set_pte_at(&init_mm, 0 /* radix unused */, ptep, new_pmd);

	return 1;
}

int pmd_clear_huge(pmd_t *pmd)
{
	if (pmd_huge(*pmd)) {
		pmd_clear(pmd);
		return 1;
	}

	return 0;
}

int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
{
	pte_t *pte;

	pte = (pte_t *)pmd_page_vaddr(*pmd);
	pmd_clear(pmd);

	flush_tlb_kernel_range(addr, addr + PMD_SIZE);

	pte_free_kernel(&init_mm, pte);

	return 1;
}

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int __init arch_ioremap_p4d_supported(void)
{
	return 0;
}