sdhci-of-esdhc.c 31.2 KB
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
 * Freescale eSDHC controller driver.
 *
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 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
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 * Copyright (c) 2009 MontaVista Software, Inc.
 *
 * Authors: Xiaobo Xie <X.Xie@freescale.com>
 *	    Anton Vorontsov <avorontsov@ru.mvista.com>
 */

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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/sys_soc.h>
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#include <linux/clk.h>
#include <linux/ktime.h>
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#include <linux/dma-mapping.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include "sdhci-pltfm.h"
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#include "sdhci-esdhc.h"
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#define VENDOR_V_22	0x12
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#define VENDOR_V_23	0x13
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#define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1)

struct esdhc_clk_fixup {
	const unsigned int sd_dflt_max_clk;
	const unsigned int max_clk[MMC_TIMING_NUM];
};

static const struct esdhc_clk_fixup ls1021a_esdhc_clk = {
	.sd_dflt_max_clk = 25000000,
	.max_clk[MMC_TIMING_MMC_HS] = 46500000,
	.max_clk[MMC_TIMING_SD_HS] = 46500000,
};

static const struct esdhc_clk_fixup ls1046a_esdhc_clk = {
	.sd_dflt_max_clk = 25000000,
	.max_clk[MMC_TIMING_UHS_SDR104] = 167000000,
	.max_clk[MMC_TIMING_MMC_HS200] = 167000000,
};

static const struct esdhc_clk_fixup ls1012a_esdhc_clk = {
	.sd_dflt_max_clk = 25000000,
	.max_clk[MMC_TIMING_UHS_SDR104] = 125000000,
	.max_clk[MMC_TIMING_MMC_HS200] = 125000000,
};

static const struct esdhc_clk_fixup p1010_esdhc_clk = {
	.sd_dflt_max_clk = 20000000,
	.max_clk[MMC_TIMING_LEGACY] = 20000000,
	.max_clk[MMC_TIMING_MMC_HS] = 42000000,
	.max_clk[MMC_TIMING_SD_HS] = 40000000,
};

static const struct of_device_id sdhci_esdhc_of_match[] = {
	{ .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
	{ .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
	{ .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
	{ .compatible = "fsl,p1010-esdhc",   .data = &p1010_esdhc_clk},
	{ .compatible = "fsl,mpc8379-esdhc" },
	{ .compatible = "fsl,mpc8536-esdhc" },
	{ .compatible = "fsl,esdhc" },
	{ }
};
MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);

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struct sdhci_esdhc {
	u8 vendor_ver;
	u8 spec_ver;
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	bool quirk_incorrect_hostver;
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	bool quirk_limited_clk_division;
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	bool quirk_unreliable_pulse_detection;
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	bool quirk_fixup_tuning;
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	bool quirk_ignore_data_inhibit;
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	unsigned int peripheral_clock;
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	const struct esdhc_clk_fixup *clk_fixup;
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	u32 div_ratio;
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};

/**
 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
 *		       to make it compatible with SD spec.
 *
 * @host: pointer to sdhci_host
 * @spec_reg: SD spec register address
 * @value: 32bit eSDHC register value on spec_reg address
 *
 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
 * registers are 32 bits. There are differences in register size, register
 * address, register function, bit position and function between eSDHC spec
 * and SD spec.
 *
 * Return a fixed up register value
 */
static u32 esdhc_readl_fixup(struct sdhci_host *host,
				     int spec_reg, u32 value)
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{
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	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
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	u32 ret;

	/*
	 * The bit of ADMA flag in eSDHC is not compatible with standard
	 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
	 * supported by eSDHC.
	 * And for many FSL eSDHC controller, the reset value of field
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	 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA,
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	 * only these vendor version is greater than 2.2/0x12 support ADMA.
	 */
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	if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
		if (esdhc->vendor_ver > VENDOR_V_22) {
			ret = value | SDHCI_CAN_DO_ADMA2;
			return ret;
		}
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	}
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	/*
	 * The DAT[3:0] line signal levels and the CMD line signal level are
	 * not compatible with standard SDHC register. The line signal levels
	 * DAT[7:0] are at bits 31:24 and the command line signal level is at
	 * bit 23. All other bits are the same as in the standard SDHC
	 * register.
	 */
	if (spec_reg == SDHCI_PRESENT_STATE) {
		ret = value & 0x000fffff;
		ret |= (value >> 4) & SDHCI_DATA_LVL_MASK;
		ret |= (value << 1) & SDHCI_CMD_LVL;
		return ret;
	}

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	/*
	 * DTS properties of mmc host are used to enable each speed mode
	 * according to soc and board capability. So clean up
	 * SDR50/SDR104/DDR50 support bits here.
	 */
	if (spec_reg == SDHCI_CAPABILITIES_1) {
		ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
				SDHCI_SUPPORT_DDR50);
		return ret;
	}

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	/*
	 * Some controllers have unreliable Data Line Active
	 * bit for commands with busy signal. This affects
	 * Command Inhibit (data) bit. Just ignore it since
	 * MMC core driver has already polled card status
	 * with CMD13 after any command with busy siganl.
	 */
	if ((spec_reg == SDHCI_PRESENT_STATE) &&
	(esdhc->quirk_ignore_data_inhibit == true)) {
		ret = value & ~SDHCI_DATA_INHIBIT;
		return ret;
	}

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	ret = value;
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	return ret;
}

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static u16 esdhc_readw_fixup(struct sdhci_host *host,
				     int spec_reg, u32 value)
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{
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	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
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	u16 ret;
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	int shift = (spec_reg & 0x2) * 8;
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	if (spec_reg == SDHCI_HOST_VERSION)
		ret = value & 0xffff;
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	else
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		ret = (value >> shift) & 0xffff;
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	/* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect
	 * vendor version and spec version information.
	 */
	if ((spec_reg == SDHCI_HOST_VERSION) &&
	    (esdhc->quirk_incorrect_hostver))
		ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
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	return ret;
}

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static u8 esdhc_readb_fixup(struct sdhci_host *host,
				     int spec_reg, u32 value)
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{
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	u8 ret;
	u8 dma_bits;
	int shift = (spec_reg & 0x3) * 8;

	ret = (value >> shift) & 0xff;
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	/*
	 * "DMA select" locates at offset 0x28 in SD specification, but on
	 * P5020 or P3041, it locates at 0x29.
	 */
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	if (spec_reg == SDHCI_HOST_CONTROL) {
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		/* DMA select is 22,23 bits in Protocol Control Register */
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		dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
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		/* fixup the result */
		ret &= ~SDHCI_CTRL_DMA_MASK;
		ret |= dma_bits;
	}
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	return ret;
}

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/**
 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be
 *			written into eSDHC register.
 *
 * @host: pointer to sdhci_host
 * @spec_reg: SD spec register address
 * @value: 8/16/32bit SD spec register value that would be written
 * @old_value: 32bit eSDHC register value on spec_reg address
 *
 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
 * registers are 32 bits. There are differences in register size, register
 * address, register function, bit position and function between eSDHC spec
 * and SD spec.
 *
 * Return a fixed up register value
 */
static u32 esdhc_writel_fixup(struct sdhci_host *host,
				     int spec_reg, u32 value, u32 old_value)
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{
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	u32 ret;

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	/*
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	 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
	 * when SYSCTL[RSTD] is set for some special operations.
	 * No any impact on other operation.
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	 */
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	if (spec_reg == SDHCI_INT_ENABLE)
		ret = value | SDHCI_INT_BLK_GAP;
	else
		ret = value;

	return ret;
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}

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static u32 esdhc_writew_fixup(struct sdhci_host *host,
				     int spec_reg, u16 value, u32 old_value)
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{
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	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	int shift = (spec_reg & 0x2) * 8;
	u32 ret;

	switch (spec_reg) {
	case SDHCI_TRANSFER_MODE:
		/*
		 * Postpone this write, we must do it together with a
		 * command write that is down below. Return old value.
		 */
		pltfm_host->xfer_mode_shadow = value;
		return old_value;
	case SDHCI_COMMAND:
		ret = (value << 16) | pltfm_host->xfer_mode_shadow;
		return ret;
	}

	ret = old_value & (~(0xffff << shift));
	ret |= (value << shift);

	if (spec_reg == SDHCI_BLOCK_SIZE) {
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		/*
		 * Two last DMA bits are reserved, and first one is used for
		 * non-standard blksz of 4096 bytes that we don't support
		 * yet. So clear the DMA boundary bits.
		 */
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		ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0));
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	}
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	return ret;
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}

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static u32 esdhc_writeb_fixup(struct sdhci_host *host,
				     int spec_reg, u8 value, u32 old_value)
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{
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	u32 ret;
	u32 dma_bits;
	u8 tmp;
	int shift = (spec_reg & 0x3) * 8;

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	/*
	 * eSDHC doesn't have a standard power control register, so we do
	 * nothing here to avoid incorrect operation.
	 */
	if (spec_reg == SDHCI_POWER_CONTROL)
		return old_value;
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	/*
	 * "DMA select" location is offset 0x28 in SD specification, but on
	 * P5020 or P3041, it's located at 0x29.
	 */
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	if (spec_reg == SDHCI_HOST_CONTROL) {
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		/*
		 * If host control register is not standard, exit
		 * this function
		 */
		if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
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			return old_value;
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		/* DMA select is 22,23 bits in Protocol Control Register */
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		dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
		ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits;
		tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
		      (old_value & SDHCI_CTRL_DMA_MASK);
		ret = (ret & (~0xff)) | tmp;

		/* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */
		ret &= ~ESDHC_HOST_CONTROL_RES;
		return ret;
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	}

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	ret = (old_value & (~(0xff << shift))) | (value << shift);
	return ret;
}

static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
{
	u32 ret;
	u32 value;

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	if (reg == SDHCI_CAPABILITIES_1)
		value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1);
	else
		value = ioread32be(host->ioaddr + reg);

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	ret = esdhc_readl_fixup(host, reg, value);

	return ret;
}

static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
{
	u32 ret;
	u32 value;

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	if (reg == SDHCI_CAPABILITIES_1)
		value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1);
	else
		value = ioread32(host->ioaddr + reg);

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	ret = esdhc_readl_fixup(host, reg, value);

	return ret;
}

static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
{
	u16 ret;
	u32 value;
	int base = reg & ~0x3;

	value = ioread32be(host->ioaddr + base);
	ret = esdhc_readw_fixup(host, reg, value);
	return ret;
}

static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
{
	u16 ret;
	u32 value;
	int base = reg & ~0x3;

	value = ioread32(host->ioaddr + base);
	ret = esdhc_readw_fixup(host, reg, value);
	return ret;
}

static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
{
	u8 ret;
	u32 value;
	int base = reg & ~0x3;

	value = ioread32be(host->ioaddr + base);
	ret = esdhc_readb_fixup(host, reg, value);
	return ret;
}

static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
{
	u8 ret;
	u32 value;
	int base = reg & ~0x3;

	value = ioread32(host->ioaddr + base);
	ret = esdhc_readb_fixup(host, reg, value);
	return ret;
}

static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
{
	u32 value;

	value = esdhc_writel_fixup(host, reg, val, 0);
	iowrite32be(value, host->ioaddr + reg);
}

static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
{
	u32 value;

	value = esdhc_writel_fixup(host, reg, val, 0);
	iowrite32(value, host->ioaddr + reg);
}

static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
{
	int base = reg & ~0x3;
	u32 value;
	u32 ret;

	value = ioread32be(host->ioaddr + base);
	ret = esdhc_writew_fixup(host, reg, val, value);
	if (reg != SDHCI_TRANSFER_MODE)
		iowrite32be(ret, host->ioaddr + base);
}

static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
{
	int base = reg & ~0x3;
	u32 value;
	u32 ret;

	value = ioread32(host->ioaddr + base);
	ret = esdhc_writew_fixup(host, reg, val, value);
	if (reg != SDHCI_TRANSFER_MODE)
		iowrite32(ret, host->ioaddr + base);
}

static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
{
	int base = reg & ~0x3;
	u32 value;
	u32 ret;

	value = ioread32be(host->ioaddr + base);
	ret = esdhc_writeb_fixup(host, reg, val, value);
	iowrite32be(ret, host->ioaddr + base);
}

static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
{
	int base = reg & ~0x3;
	u32 value;
	u32 ret;

	value = ioread32(host->ioaddr + base);
	ret = esdhc_writeb_fixup(host, reg, val, value);
	iowrite32(ret, host->ioaddr + base);
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}

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/*
 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA
 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
 * and Block Gap Event(IRQSTAT[BGE]) are also set.
 * For Continue, apply soft reset for data(SYSCTL[RSTD]);
 * and re-issue the entire read transaction from beginning.
 */
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static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
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{
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	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
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	bool applicable;
	dma_addr_t dmastart;
	dma_addr_t dmanow;

	applicable = (intmask & SDHCI_INT_DATA_END) &&
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		     (intmask & SDHCI_INT_BLK_GAP) &&
		     (esdhc->vendor_ver == VENDOR_V_23);
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	if (!applicable)
		return;

	host->data->error = 0;
	dmastart = sg_dma_address(host->data->sg);
	dmanow = dmastart + host->data->bytes_xfered;
	/*
	 * Force update to the next DMA block boundary.
	 */
	dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
		SDHCI_DEFAULT_BOUNDARY_SIZE;
	host->data->bytes_xfered = dmanow - dmastart;
	sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
}

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static int esdhc_of_enable_dma(struct sdhci_host *host)
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{
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	u32 value;
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	struct device *dev = mmc_dev(host->mmc);

	if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") ||
	    of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc"))
		dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
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	value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
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	if (of_dma_is_coherent(dev->of_node))
		value |= ESDHC_DMA_SNOOP;
	else
		value &= ~ESDHC_DMA_SNOOP;

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	sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
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	return 0;
}

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static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
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{
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	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
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	if (esdhc->peripheral_clock)
		return esdhc->peripheral_clock;
	else
		return pltfm_host->clock;
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}

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static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
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{
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	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
	unsigned int clock;
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	if (esdhc->peripheral_clock)
		clock = esdhc->peripheral_clock;
	else
		clock = pltfm_host->clock;
	return clock / 256 / 16;
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}

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static void esdhc_clock_enable(struct sdhci_host *host, bool enable)
{
	u32 val;
	ktime_t timeout;

	val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);

	if (enable)
		val |= ESDHC_CLOCK_SDCLKEN;
	else
		val &= ~ESDHC_CLOCK_SDCLKEN;

	sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);

	/* Wait max 20 ms */
	timeout = ktime_add_ms(ktime_get(), 20);
	val = ESDHC_CLOCK_STABLE;
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	while  (1) {
		bool timedout = ktime_after(ktime_get(), timeout);

		if (sdhci_readl(host, ESDHC_PRSSTAT) & val)
			break;
		if (timedout) {
555
556
557
558
559
560
561
562
			pr_err("%s: Internal clock never stabilised.\n",
				mmc_hostname(host->mmc));
			break;
		}
		udelay(10);
	}
}

563
564
static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
{
565
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
566
	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
567
	int pre_div = 1;
568
	int div = 1;
569
	int division;
570
	ktime_t timeout;
571
	long fixup = 0;
572
573
	u32 temp;

574
575
	host->mmc->actual_clock = 0;

576
577
	if (clock == 0) {
		esdhc_clock_enable(host, false);
578
		return;
579
	}
580

581
	/* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
582
	if (esdhc->vendor_ver < VENDOR_V_23)
583
584
		pre_div = 2;

585
586
587
588
589
	if (host->mmc->card && mmc_card_sd(host->mmc->card) &&
		esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY)
		fixup = esdhc->clk_fixup->sd_dflt_max_clk;
	else if (esdhc->clk_fixup)
		fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];
590

591
592
	if (fixup && clock > fixup)
		clock = fixup;
593

594
	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
595
596
	temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
		  ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
597
598
599
600
601
602
603
604
	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);

	while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
		pre_div *= 2;

	while (host->max_clk / pre_div / div > clock && div < 16)
		div++;

605
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611
612
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615
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617
618
619
	if (esdhc->quirk_limited_clk_division &&
	    clock == MMC_HS200_MAX_DTR &&
	    (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 ||
	     host->flags & SDHCI_HS400_TUNING)) {
		division = pre_div * div;
		if (division <= 4) {
			pre_div = 4;
			div = 1;
		} else if (division <= 8) {
			pre_div = 4;
			div = 2;
		} else if (division <= 12) {
			pre_div = 4;
			div = 3;
		} else {
620
			pr_warn("%s: using unsupported clock division.\n",
621
622
623
624
				mmc_hostname(host->mmc));
		}
	}

625
	dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
626
		clock, host->max_clk / pre_div / div);
627
	host->mmc->actual_clock = host->max_clk / pre_div / div;
628
	esdhc->div_ratio = pre_div * div;
629
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631
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634
635
636
	pre_div >>= 1;
	div--;

	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
	temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
		| (div << ESDHC_DIVIDER_SHIFT)
		| (pre_div << ESDHC_PREDIV_SHIFT));
	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
637

638
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641
642
643
644
645
646
	if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
	    clock == MMC_HS200_MAX_DTR) {
		temp = sdhci_readl(host, ESDHC_TBCTL);
		sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL);
		temp = sdhci_readl(host, ESDHC_SDCLKCTL);
		sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL);
		esdhc_clock_enable(host, true);

		temp = sdhci_readl(host, ESDHC_DLLCFG0);
647
648
649
		temp |= ESDHC_DLL_ENABLE;
		if (host->mmc->actual_clock == MMC_HS200_MAX_DTR)
			temp |= ESDHC_DLL_FREQ_SEL;
650
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652
653
654
655
656
657
658
659
		sdhci_writel(host, temp, ESDHC_DLLCFG0);
		temp = sdhci_readl(host, ESDHC_TBCTL);
		sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL);

		esdhc_clock_enable(host, false);
		temp = sdhci_readl(host, ESDHC_DMA_SYSCTL);
		temp |= ESDHC_FLUSH_ASYNC_FIFO;
		sdhci_writel(host, temp, ESDHC_DMA_SYSCTL);
	}

660
	/* Wait max 20 ms */
661
	timeout = ktime_add_ms(ktime_get(), 20);
662
663
664
665
666
667
	while (1) {
		bool timedout = ktime_after(ktime_get(), timeout);

		if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
			break;
		if (timedout) {
668
669
670
671
			pr_err("%s: Internal clock never stabilised.\n",
				mmc_hostname(host->mmc));
			return;
		}
672
		udelay(10);
673
674
	}

675
	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
676
677
	temp |= ESDHC_CLOCK_SDCLKEN;
	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
678
679
}

680
static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
681
682
683
{
	u32 ctrl;

684
685
	ctrl = sdhci_readl(host, ESDHC_PROCTL);
	ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK);
686
687
	switch (width) {
	case MMC_BUS_WIDTH_8:
688
		ctrl |= ESDHC_CTRL_8BITBUS;
689
690
691
		break;

	case MMC_BUS_WIDTH_4:
692
		ctrl |= ESDHC_CTRL_4BITBUS;
693
694
695
696
697
698
		break;

	default:
		break;
	}

699
	sdhci_writel(host, ctrl, ESDHC_PROCTL);
700
701
}

702
703
static void esdhc_reset(struct sdhci_host *host, u8 mask)
{
704
705
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
706
707
	u32 val;

708
709
710
711
	sdhci_reset(host, mask);

	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
712

713
714
715
	if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc"))
		mdelay(5);

716
717
718
719
	if (mask & SDHCI_RESET_ALL) {
		val = sdhci_readl(host, ESDHC_TBCTL);
		val &= ~ESDHC_TB_EN;
		sdhci_writel(host, val, ESDHC_TBCTL);
720
721
722
723
724
725

		if (esdhc->quirk_unreliable_pulse_detection) {
			val = sdhci_readl(host, ESDHC_DLLCFG1);
			val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL;
			sdhci_writel(host, val, ESDHC_DLLCFG1);
		}
726
	}
727
728
}

729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
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761
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763
764
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766
767
768
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772
773
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775
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777
778
779
780
781
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783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
/* The SCFG, Supplemental Configuration Unit, provides SoC specific
 * configuration and status registers for the device. There is a
 * SDHC IO VSEL control register on SCFG for some platforms. It's
 * used to support SDHC IO voltage switching.
 */
static const struct of_device_id scfg_device_ids[] = {
	{ .compatible = "fsl,t1040-scfg", },
	{ .compatible = "fsl,ls1012a-scfg", },
	{ .compatible = "fsl,ls1046a-scfg", },
	{}
};

/* SDHC IO VSEL control register definition */
#define SCFG_SDHCIOVSELCR	0x408
#define SDHCIOVSELCR_TGLEN	0x80000000
#define SDHCIOVSELCR_VSELVAL	0x60000000
#define SDHCIOVSELCR_SDHC_VS	0x00000001

static int esdhc_signal_voltage_switch(struct mmc_host *mmc,
				       struct mmc_ios *ios)
{
	struct sdhci_host *host = mmc_priv(mmc);
	struct device_node *scfg_node;
	void __iomem *scfg_base = NULL;
	u32 sdhciovselcr;
	u32 val;

	/*
	 * Signal Voltage Switching is only applicable for Host Controllers
	 * v3.00 and above.
	 */
	if (host->version < SDHCI_SPEC_300)
		return 0;

	val = sdhci_readl(host, ESDHC_PROCTL);

	switch (ios->signal_voltage) {
	case MMC_SIGNAL_VOLTAGE_330:
		val &= ~ESDHC_VOLT_SEL;
		sdhci_writel(host, val, ESDHC_PROCTL);
		return 0;
	case MMC_SIGNAL_VOLTAGE_180:
		scfg_node = of_find_matching_node(NULL, scfg_device_ids);
		if (scfg_node)
			scfg_base = of_iomap(scfg_node, 0);
		if (scfg_base) {
			sdhciovselcr = SDHCIOVSELCR_TGLEN |
				       SDHCIOVSELCR_VSELVAL;
			iowrite32be(sdhciovselcr,
				scfg_base + SCFG_SDHCIOVSELCR);

			val |= ESDHC_VOLT_SEL;
			sdhci_writel(host, val, ESDHC_PROCTL);
			mdelay(5);

			sdhciovselcr = SDHCIOVSELCR_TGLEN |
				       SDHCIOVSELCR_SDHC_VS;
			iowrite32be(sdhciovselcr,
				scfg_base + SCFG_SDHCIOVSELCR);
			iounmap(scfg_base);
		} else {
			val |= ESDHC_VOLT_SEL;
			sdhci_writel(host, val, ESDHC_PROCTL);
		}
		return 0;
	default:
		return 0;
	}
}

799
800
801
802
803
804
805
806
807
808
809
810
811
static struct soc_device_attribute soc_fixup_tuning[] = {
	{ .family = "QorIQ T1040", .revision = "1.0", },
	{ .family = "QorIQ T2080", .revision = "1.0", },
	{ .family = "QorIQ T1023", .revision = "1.0", },
	{ .family = "QorIQ LS1021A", .revision = "1.0", },
	{ .family = "QorIQ LS1080A", .revision = "1.0", },
	{ .family = "QorIQ LS2080A", .revision = "1.0", },
	{ .family = "QorIQ LS1012A", .revision = "1.0", },
	{ .family = "QorIQ LS1043A", .revision = "1.*", },
	{ .family = "QorIQ LS1046A", .revision = "1.0", },
	{ },
};

812
static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable)
813
814
815
816
{
	u32 val;

	esdhc_clock_enable(host, false);
817

818
819
820
821
822
	val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
	val |= ESDHC_FLUSH_ASYNC_FIFO;
	sdhci_writel(host, val, ESDHC_DMA_SYSCTL);

	val = sdhci_readl(host, ESDHC_TBCTL);
823
824
825
826
	if (enable)
		val |= ESDHC_TB_EN;
	else
		val &= ~ESDHC_TB_EN;
827
	sdhci_writel(host, val, ESDHC_TBCTL);
828

829
	esdhc_clock_enable(host, true);
830
831
832
833
834
835
836
837
}

static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
{
	struct sdhci_host *host = mmc_priv(mmc);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
	bool hs400_tuning;
838
	unsigned int clk;
839
840
841
	u32 val;
	int ret;

842
843
844
845
846
847
848
	/* For tuning mode, the sd clock divisor value
	 * must be larger than 3 according to reference manual.
	 */
	clk = esdhc->peripheral_clock / 3;
	if (host->clock > clk)
		esdhc_of_set_clock(host, clk);

849
850
851
852
	if (esdhc->quirk_limited_clk_division &&
	    host->flags & SDHCI_HS400_TUNING)
		esdhc_of_set_clock(host, host->clock);

853
854
855
856
857
858
859
860
861
862
	esdhc_tuning_block_enable(host, true);

	hs400_tuning = host->flags & SDHCI_HS400_TUNING;
	ret = sdhci_execute_tuning(mmc, opcode);

	if (hs400_tuning) {
		val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
		val |= ESDHC_FLW_CTL_BG;
		sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
	}
863

864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
	if (host->tuning_err == -EAGAIN && esdhc->quirk_fixup_tuning) {

		/* program TBPTR[TB_WNDW_END_PTR] = 3*DIV_RATIO and
		 * program TBPTR[TB_WNDW_START_PTR] = 5*DIV_RATIO
		 */
		val = sdhci_readl(host, ESDHC_TBPTR);
		val = (val & ~((0x7f << 8) | 0x7f)) |
		(3 * esdhc->div_ratio) | ((5 * esdhc->div_ratio) << 8);
		sdhci_writel(host, val, ESDHC_TBPTR);

		/* program the software tuning mode by setting
		 * TBCTL[TB_MODE]=2'h3
		 */
		val = sdhci_readl(host, ESDHC_TBCTL);
		val |= 0x3;
		sdhci_writel(host, val, ESDHC_TBCTL);
		sdhci_execute_tuning(mmc, opcode);
	}
882
883
884
885
886
887
888
889
890
891
	return ret;
}

static void esdhc_set_uhs_signaling(struct sdhci_host *host,
				   unsigned int timing)
{
	if (timing == MMC_TIMING_MMC_HS400)
		esdhc_tuning_block_enable(host, true);
	else
		sdhci_set_uhs_signaling(host, timing);
892
893
}

894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
static u32 esdhc_irq(struct sdhci_host *host, u32 intmask)
{
	u32 command;

	if (of_find_compatible_node(NULL, NULL,
				"fsl,p2020-esdhc")) {
		command = SDHCI_GET_CMD(sdhci_readw(host,
					SDHCI_COMMAND));
		if (command == MMC_WRITE_MULTIPLE_BLOCK &&
				sdhci_readw(host, SDHCI_BLOCK_COUNT) &&
				intmask & SDHCI_INT_DATA_END) {
			intmask &= ~SDHCI_INT_DATA_END;
			sdhci_writel(host, SDHCI_INT_DATA_END,
					SDHCI_INT_STATUS);
		}
	}
	return intmask;
}

913
#ifdef CONFIG_PM_SLEEP
914
915
916
917
918
static u32 esdhc_proctl;
static int esdhc_of_suspend(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);

919
	esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
920

921
922
923
	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
		mmc_retune_needed(host->mmc);

924
925
926
	return sdhci_suspend_host(host);
}

927
static int esdhc_of_resume(struct device *dev)
928
929
930
931
932
933
934
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	int ret = sdhci_resume_host(host);

	if (ret == 0) {
		/* Isn't this already done by sdhci_resume_host() ? --rmk */
		esdhc_of_enable_dma(host);
935
		sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
936
937
938
939
940
	}
	return ret;
}
#endif

941
942
943
944
static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops,
			esdhc_of_suspend,
			esdhc_of_resume);

945
946
947
948
949
950
951
952
953
954
955
956
957
958
static const struct sdhci_ops sdhci_esdhc_be_ops = {
	.read_l = esdhc_be_readl,
	.read_w = esdhc_be_readw,
	.read_b = esdhc_be_readb,
	.write_l = esdhc_be_writel,
	.write_w = esdhc_be_writew,
	.write_b = esdhc_be_writeb,
	.set_clock = esdhc_of_set_clock,
	.enable_dma = esdhc_of_enable_dma,
	.get_max_clock = esdhc_of_get_max_clock,
	.get_min_clock = esdhc_of_get_min_clock,
	.adma_workaround = esdhc_of_adma_workaround,
	.set_bus_width = esdhc_pltfm_set_bus_width,
	.reset = esdhc_reset,
959
	.set_uhs_signaling = esdhc_set_uhs_signaling,
960
	.irq = esdhc_irq,
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
};

static const struct sdhci_ops sdhci_esdhc_le_ops = {
	.read_l = esdhc_le_readl,
	.read_w = esdhc_le_readw,
	.read_b = esdhc_le_readb,
	.write_l = esdhc_le_writel,
	.write_w = esdhc_le_writew,
	.write_b = esdhc_le_writeb,
	.set_clock = esdhc_of_set_clock,
	.enable_dma = esdhc_of_enable_dma,
	.get_max_clock = esdhc_of_get_max_clock,
	.get_min_clock = esdhc_of_get_min_clock,
	.adma_workaround = esdhc_of_adma_workaround,
	.set_bus_width = esdhc_pltfm_set_bus_width,
	.reset = esdhc_reset,
977
	.set_uhs_signaling = esdhc_set_uhs_signaling,
978
	.irq = esdhc_irq,
979
980
981
};

static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
982
983
984
985
986
987
	.quirks = ESDHC_DEFAULT_QUIRKS |
#ifdef CONFIG_PPC
		  SDHCI_QUIRK_BROKEN_CARD_DETECTION |
#endif
		  SDHCI_QUIRK_NO_CARD_NO_RESET |
		  SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
988
989
990
991
	.ops = &sdhci_esdhc_be_ops,
};

static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
992
993
994
	.quirks = ESDHC_DEFAULT_QUIRKS |
		  SDHCI_QUIRK_NO_CARD_NO_RESET |
		  SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
995
	.ops = &sdhci_esdhc_le_ops,
996
};
997

998
999
1000
1001
1002
1003
static struct soc_device_attribute soc_incorrect_hostver[] = {
	{ .family = "QorIQ T4240", .revision = "1.0", },
	{ .family = "QorIQ T4240", .revision = "2.0", },
	{ },
};

1004
1005
static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = {
	{ .family = "QorIQ LX2160A", .revision = "1.0", },
1006
	{ .family = "QorIQ LX2160A", .revision = "2.0", },
1007
	{ .family = "QorIQ LS1028A", .revision = "1.0", },
1008
1009
1010
	{ },
};

1011
1012
1013
1014
1015
static struct soc_device_attribute soc_unreliable_pulse_detection[] = {
	{ .family = "QorIQ LX2160A", .revision = "1.0", },
	{ },
};

1016
1017
static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
{
1018
	const struct of_device_id *match;
1019
1020
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_esdhc *esdhc;
1021
1022
1023
	struct device_node *np;
	struct clk *clk;
	u32 val;
1024
1025
1026
	u16 host_ver;

	pltfm_host = sdhci_priv(host);
1027
	esdhc = sdhci_pltfm_priv(pltfm_host);
1028
1029
1030
1031
1032

	host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
	esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
			     SDHCI_VENDOR_VER_SHIFT;
	esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
1033
1034
1035
1036
	if (soc_device_match(soc_incorrect_hostver))
		esdhc->quirk_incorrect_hostver = true;
	else
		esdhc->quirk_incorrect_hostver = false;
1037

1038
1039
1040
1041
1042
	if (soc_device_match(soc_fixup_sdhc_clkdivs))
		esdhc->quirk_limited_clk_division = true;
	else
		esdhc->quirk_limited_clk_division = false;

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	if (soc_device_match(soc_unreliable_pulse_detection))
		esdhc->quirk_unreliable_pulse_detection = true;
	else
		esdhc->quirk_unreliable_pulse_detection = false;

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	match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node);
	if (match)
		esdhc->clk_fixup = match->data;
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	np = pdev->dev.of_node;
	clk = of_clk_get(np, 0);
	if (!IS_ERR(clk)) {
		/*
		 * esdhc->peripheral_clock would be assigned with a value
		 * which is eSDHC base clock when use periperal clock.
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		 * For some platforms, the clock value got by common clk
		 * API is peripheral clock while the eSDHC base clock is
		 * 1/2 peripheral clock.
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		 */
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		if (of_device_is_compatible(np, "fsl,ls1046a-esdhc") ||
		    of_device_is_compatible(np, "fsl,ls1028a-esdhc"))
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			esdhc->peripheral_clock = clk_get_rate(clk) / 2;
		else
			esdhc->peripheral_clock = clk_get_rate(clk);

		clk_put(clk);
	}

	if (esdhc->peripheral_clock) {
		esdhc_clock_enable(host, false);
		val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
		val |= ESDHC_PERIPHERAL_CLK_SEL;
		sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
		esdhc_clock_enable(host, true);
	}
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}

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static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc)
{
	esdhc_tuning_block_enable(mmc_priv(mmc), false);
	return 0;
}

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Bill Pemberton committed
1085
static int sdhci_esdhc_probe(struct platform_device *pdev)
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{
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	struct sdhci_host *host;
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	struct device_node *np;
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	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_esdhc *esdhc;
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	int ret;

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	np = pdev->dev.of_node;

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	if (of_property_read_bool(np, "little-endian"))
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		host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata,
					sizeof(struct sdhci_esdhc));
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	else
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		host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata,
					sizeof(struct sdhci_esdhc));
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	if (IS_ERR(host))
		return PTR_ERR(host);

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	host->mmc_host_ops.start_signal_voltage_switch =
		esdhc_signal_voltage_switch;
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	host->mmc_host_ops.execute_tuning = esdhc_execute_tuning;
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	host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr;
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	host->tuning_delay = 1;
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	esdhc_init(pdev, host);

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	sdhci_get_of_property(pdev);

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	pltfm_host = sdhci_priv(host);
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	esdhc = sdhci_pltfm_priv(pltfm_host);
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	if (soc_device_match(soc_fixup_tuning))
		esdhc->quirk_fixup_tuning = true;
	else
		esdhc->quirk_fixup_tuning = false;

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	if (esdhc->vendor_ver == VENDOR_V_22)
		host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;

	if (esdhc->vendor_ver > VENDOR_V_22)
		host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;

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	if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) {
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		host->quirks2 |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
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		host->quirks2 |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
	}
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	if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
	    of_device_is_compatible(np, "fsl,p5020-esdhc") ||
	    of_device_is_compatible(np, "fsl,p4080-esdhc") ||
	    of_device_is_compatible(np, "fsl,p1020-esdhc") ||
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	    of_device_is_compatible(np, "fsl,t1040-esdhc"))
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		host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;

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	if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
		host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;

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	esdhc->quirk_ignore_data_inhibit = false;
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	if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
		/*
		 * Freescale messed up with P2020 as it has a non-standard
		 * host control register
		 */
		host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
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		esdhc->quirk_ignore_data_inhibit = true;
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	}

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	/* call to generic mmc_of_parse to support additional capabilities */
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	ret = mmc_of_parse(host->mmc);
	if (ret)
		goto err;

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	mmc_of_parse_voltage(np, &host->ocr_mask);
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	ret = sdhci_add_host(host);
	if (ret)
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		goto err;
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	return 0;
 err:
	sdhci_pltfm_free(pdev);
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	return ret;
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}

static struct platform_driver sdhci_esdhc_driver = {
	.driver = {
		.name = "sdhci-esdhc",
		.of_match_table = sdhci_esdhc_of_match,
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		.pm = &esdhc_of_dev_pm_ops,
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	},
	.probe = sdhci_esdhc_probe,
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	.remove = sdhci_pltfm_unregister,
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};

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module_platform_driver(sdhci_esdhc_driver);
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MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
	      "Anton Vorontsov <avorontsov@ru.mvista.com>");
MODULE_LICENSE("GPL v2");