sdhci-pci-core.c 52.8 KB
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*  linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
 *
 *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
 *
 * Thanks to the following companies for their support:
 *
 *     - JMicron (hardware and technical support)
 */

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#include <linux/bitfield.h>
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#include <linux/string.h>
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#include <linux/delay.h>
#include <linux/highmem.h>
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#include <linux/module.h>
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#include <linux/pci.h>
#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include <linux/scatterlist.h>
#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/pm_runtime.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/mmc/sdhci-pci-data.h>
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#include <linux/acpi.h>
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#ifdef CONFIG_X86
#include <asm/iosf_mbi.h>
#endif

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#include "cqhci.h"

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#include "sdhci.h"
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#include "sdhci-pci.h"
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static void sdhci_pci_hw_reset(struct sdhci_host *host);

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#ifdef CONFIG_PM_SLEEP
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static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
{
	mmc_pm_flag_t pm_flags = 0;
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	bool cap_cd_wake = false;
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	int i;

	for (i = 0; i < chip->num_slots; i++) {
		struct sdhci_pci_slot *slot = chip->slots[i];

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		if (slot) {
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			pm_flags |= slot->host->mmc->pm_flags;
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			if (slot->host->mmc->caps & MMC_CAP_CD_WAKE)
				cap_cd_wake = true;
		}
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	}

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	if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ))
		return device_wakeup_enable(&chip->pdev->dev);
	else if (!cap_cd_wake)
		return device_wakeup_disable(&chip->pdev->dev);

	return 0;
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}

static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
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{
	int i, ret;

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	sdhci_pci_init_wakeup(chip);

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	for (i = 0; i < chip->num_slots; i++) {
		struct sdhci_pci_slot *slot = chip->slots[i];
		struct sdhci_host *host;

		if (!slot)
			continue;

		host = slot->host;

		if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
			mmc_retune_needed(host->mmc);

		ret = sdhci_suspend_host(host);
		if (ret)
			goto err_pci_suspend;
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		if (device_may_wakeup(&chip->pdev->dev))
			mmc_gpio_set_cd_wake(host->mmc, true);
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	}

	return 0;

err_pci_suspend:
	while (--i >= 0)
		sdhci_resume_host(chip->slots[i]->host);
	return ret;
}

int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
{
	struct sdhci_pci_slot *slot;
	int i, ret;

	for (i = 0; i < chip->num_slots; i++) {
		slot = chip->slots[i];
		if (!slot)
			continue;

		ret = sdhci_resume_host(slot->host);
		if (ret)
			return ret;
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		mmc_gpio_set_cd_wake(slot->host->mmc, false);
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	}

	return 0;
}
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static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
{
	int ret;

	ret = cqhci_suspend(chip->slots[0]->host->mmc);
	if (ret)
		return ret;

	return sdhci_pci_suspend_host(chip);
}

static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
{
	int ret;

	ret = sdhci_pci_resume_host(chip);
	if (ret)
		return ret;

	return cqhci_resume(chip->slots[0]->host->mmc);
}
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#endif

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#ifdef CONFIG_PM
static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
{
	struct sdhci_pci_slot *slot;
	struct sdhci_host *host;
	int i, ret;

	for (i = 0; i < chip->num_slots; i++) {
		slot = chip->slots[i];
		if (!slot)
			continue;

		host = slot->host;

		ret = sdhci_runtime_suspend_host(host);
		if (ret)
			goto err_pci_runtime_suspend;

		if (chip->rpm_retune &&
		    host->tuning_mode != SDHCI_TUNING_MODE_3)
			mmc_retune_needed(host->mmc);
	}

	return 0;

err_pci_runtime_suspend:
	while (--i >= 0)
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		sdhci_runtime_resume_host(chip->slots[i]->host, 0);
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	return ret;
}

static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
{
	struct sdhci_pci_slot *slot;
	int i, ret;

	for (i = 0; i < chip->num_slots; i++) {
		slot = chip->slots[i];
		if (!slot)
			continue;

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		ret = sdhci_runtime_resume_host(slot->host, 0);
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		if (ret)
			return ret;
	}

	return 0;
}
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static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
{
	int ret;

	ret = cqhci_suspend(chip->slots[0]->host->mmc);
	if (ret)
		return ret;

	return sdhci_pci_runtime_suspend_host(chip);
}

static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
{
	int ret;

	ret = sdhci_pci_runtime_resume_host(chip);
	if (ret)
		return ret;

	return cqhci_resume(chip->slots[0]->host->mmc);
}
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#endif

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static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
{
	int cmd_error = 0;
	int data_error = 0;

	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
		return intmask;

	cqhci_irq(host->mmc, intmask, cmd_error, data_error);

	return 0;
}

static void sdhci_pci_dumpregs(struct mmc_host *mmc)
{
	sdhci_dumpregs(mmc_priv(mmc));
}

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/*****************************************************************************\
 *                                                                           *
 * Hardware specific quirk handling                                          *
 *                                                                           *
\*****************************************************************************/

static int ricoh_probe(struct sdhci_pci_chip *chip)
{
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	if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
	    chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
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		chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
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	return 0;
}

static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
{
	slot->host->caps =
		((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
			& SDHCI_TIMEOUT_CLK_MASK) |
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		((0x21 << SDHCI_CLOCK_BASE_SHIFT)
			& SDHCI_CLOCK_BASE_MASK) |

		SDHCI_TIMEOUT_CLK_UNIT |
		SDHCI_CAN_VDD_330 |
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		SDHCI_CAN_DO_HISPD |
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		SDHCI_CAN_DO_SDMA;
	return 0;
}

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#ifdef CONFIG_PM_SLEEP
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static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
{
	/* Apply a delay to allow controller to settle */
	/* Otherwise it becomes confused if card state changed
		during suspend */
	msleep(500);
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	return sdhci_pci_resume_host(chip);
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}
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#endif
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static const struct sdhci_pci_fixes sdhci_ricoh = {
	.probe		= ricoh_probe,
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	.quirks		= SDHCI_QUIRK_32BIT_DMA_ADDR |
			  SDHCI_QUIRK_FORCE_DMA |
			  SDHCI_QUIRK_CLOCK_BEFORE_RESET,
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};

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static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
	.probe_slot	= ricoh_mmc_probe_slot,
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#ifdef CONFIG_PM_SLEEP
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	.resume		= ricoh_mmc_resume,
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#endif
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	.quirks		= SDHCI_QUIRK_32BIT_DMA_ADDR |
			  SDHCI_QUIRK_CLOCK_BEFORE_RESET |
			  SDHCI_QUIRK_NO_CARD_NO_RESET |
			  SDHCI_QUIRK_MISSING_CAPS
};

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static const struct sdhci_pci_fixes sdhci_ene_712 = {
	.quirks		= SDHCI_QUIRK_SINGLE_POWER_WRITE |
			  SDHCI_QUIRK_BROKEN_DMA,
};

static const struct sdhci_pci_fixes sdhci_ene_714 = {
	.quirks		= SDHCI_QUIRK_SINGLE_POWER_WRITE |
			  SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
			  SDHCI_QUIRK_BROKEN_DMA,
};

static const struct sdhci_pci_fixes sdhci_cafe = {
	.quirks		= SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
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			  SDHCI_QUIRK_NO_BUSY_IRQ |
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			  SDHCI_QUIRK_BROKEN_CARD_DETECTION |
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			  SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
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};

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static const struct sdhci_pci_fixes sdhci_intel_qrk = {
	.quirks		= SDHCI_QUIRK_NO_HISPD_BIT,
};

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static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
{
	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
	return 0;
}

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/*
 * ADMA operation is disabled for Moorestown platform due to
 * hardware bugs.
 */
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static int mrst_hc_probe(struct sdhci_pci_chip *chip)
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{
	/*
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	 * slots number is fixed here for MRST as SDIO3/5 are never used and
	 * have hardware bugs.
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	 */
	chip->num_slots = 1;
	return 0;
}

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static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
{
	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
	return 0;
}

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#ifdef CONFIG_PM
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static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
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{
	struct sdhci_pci_slot *slot = dev_id;
	struct sdhci_host *host = slot->host;

	mmc_detect_change(host->mmc, msecs_to_jiffies(200));
	return IRQ_HANDLED;
}

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static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
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{
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	int err, irq, gpio = slot->cd_gpio;
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	slot->cd_gpio = -EINVAL;
	slot->cd_irq = -EINVAL;

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	if (!gpio_is_valid(gpio))
		return;

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	err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
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	if (err < 0)
		goto out;

	err = gpio_direction_input(gpio);
	if (err < 0)
		goto out_free;

	irq = gpio_to_irq(gpio);
	if (irq < 0)
		goto out_free;

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	err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
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			  IRQF_TRIGGER_FALLING, "sd_cd", slot);
	if (err)
		goto out_free;

	slot->cd_gpio = gpio;
	slot->cd_irq = irq;

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	return;
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out_free:
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	devm_gpio_free(&slot->chip->pdev->dev, gpio);
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out:
	dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
}

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static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
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{
	if (slot->cd_irq >= 0)
		free_irq(slot->cd_irq, slot);
}

#else

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static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
{
}

static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
{
}
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#endif

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static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
{
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	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
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	slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
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	return 0;
}

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static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
{
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	slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
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	return 0;
}

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static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
	.quirks		= SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
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	.probe_slot	= mrst_hc_probe_slot,
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};

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static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
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	.quirks		= SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
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	.probe		= mrst_hc_probe,
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};

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static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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	.allow_runtime_pm = true,
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	.own_cd_for_runtime_pm = true,
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};

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static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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	.quirks2	= SDHCI_QUIRK2_HOST_OFF_CARD_ON,
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	.allow_runtime_pm = true,
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	.probe_slot	= mfd_sdio_probe_slot,
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};

static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
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	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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	.allow_runtime_pm = true,
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	.probe_slot	= mfd_emmc_probe_slot,
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};

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static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
	.quirks		= SDHCI_QUIRK_BROKEN_ADMA,
	.probe_slot	= pch_hc_probe_slot,
};

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#ifdef CONFIG_X86

#define BYT_IOSF_SCCEP			0x63
#define BYT_IOSF_OCP_NETCTRL0		0x1078
#define BYT_IOSF_OCP_TIMEOUT_BASE	GENMASK(10, 8)

static void byt_ocp_setting(struct pci_dev *pdev)
{
	u32 val = 0;

	if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC &&
	    pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO &&
	    pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD &&
	    pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2)
		return;

	if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
			  &val)) {
		dev_err(&pdev->dev, "%s read error\n", __func__);
		return;
	}

	if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
		return;

	val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;

	if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
			   val)) {
		dev_err(&pdev->dev, "%s write error\n", __func__);
		return;
	}

	dev_dbg(&pdev->dev, "%s completed\n", __func__);
}

#else

static inline void byt_ocp_setting(struct pci_dev *pdev)
{
}

#endif

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enum {
	INTEL_DSM_FNS		=  0,
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	INTEL_DSM_V18_SWITCH	=  3,
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	INTEL_DSM_V33_SWITCH	=  4,
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	INTEL_DSM_DRV_STRENGTH	=  9,
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	INTEL_DSM_D3_RETUNE	= 10,
};

struct intel_host {
	u32	dsm_fns;
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	int	drv_strength;
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	bool	d3_retune;
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	bool	rpm_retune_ok;
	u32	glk_rx_ctrl1;
	u32	glk_tun_val;
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};

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static const guid_t intel_dsm_guid =
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	GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
		  0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
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static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
		       unsigned int fn, u32 *result)
{
	union acpi_object *obj;
	int err = 0;
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	size_t len;
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	obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
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	if (!obj)
		return -EOPNOTSUPP;

	if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
		err = -EINVAL;
		goto out;
	}

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	len = min_t(size_t, obj->buffer.length, 4);

	*result = 0;
	memcpy(result, obj->buffer.pointer, len);
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out:
	ACPI_FREE(obj);

	return err;
}

static int intel_dsm(struct intel_host *intel_host, struct device *dev,
		     unsigned int fn, u32 *result)
{
	if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
		return -EOPNOTSUPP;

	return __intel_dsm(intel_host, dev, fn, result);
}

static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
			   struct mmc_host *mmc)
{
	int err;
	u32 val;

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	intel_host->d3_retune = true;

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	err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
	if (err) {
		pr_debug("%s: DSM not supported, error %d\n",
			 mmc_hostname(mmc), err);
		return;
	}

	pr_debug("%s: DSM function mask %#x\n",
		 mmc_hostname(mmc), intel_host->dsm_fns);

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	err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
	intel_host->drv_strength = err ? 0 : val;

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	err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
	intel_host->d3_retune = err ? true : !!val;
}

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static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
{
	u8 reg;

	reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
	reg |= 0x10;
	sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
	/* For eMMC, minimum is 1us but give it 9us for good measure */
	udelay(9);
	reg &= ~0x10;
	sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
	/* For eMMC, minimum is 200us but give it 300us for good measure */
	usleep_range(300, 1000);
}

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static int intel_select_drive_strength(struct mmc_card *card,
				       unsigned int max_dtr, int host_drv,
				       int card_drv, int *drv_type)
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{
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	struct sdhci_host *host = mmc_priv(card->host);
	struct sdhci_pci_slot *slot = sdhci_priv(host);
	struct intel_host *intel_host = sdhci_pci_priv(slot);
601

602
	return intel_host->drv_strength;
603
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}

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static int bxt_get_cd(struct mmc_host *mmc)
{
	int gpio_cd = mmc_gpio_get_cd(mmc);
	struct sdhci_host *host = mmc_priv(mmc);
	unsigned long flags;
	int ret = 0;

	if (!gpio_cd)
		return 0;

	spin_lock_irqsave(&host->lock, flags);

	if (host->flags & SDHCI_DEVICE_DEAD)
		goto out;

	ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
out:
	spin_unlock_irqrestore(&host->lock, flags);

	return ret;
}

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#define SDHCI_INTEL_PWR_TIMEOUT_CNT	20
#define SDHCI_INTEL_PWR_TIMEOUT_UDELAY	100

static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
				  unsigned short vdd)
{
	int cntr;
	u8 reg;

	sdhci_set_power(host, mode, vdd);

	if (mode == MMC_POWER_OFF)
		return;

	/*
	 * Bus power might not enable after D3 -> D0 transition due to the
	 * present state not yet having propagated. Retry for up to 2ms.
	 */
	for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
		reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
		if (reg & SDHCI_POWER_ON)
			break;
		udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
		reg |= SDHCI_POWER_ON;
		sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
	}
}

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#define INTEL_HS400_ES_REG 0x78
#define INTEL_HS400_ES_BIT BIT(0)

static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
					struct mmc_ios *ios)
{
	struct sdhci_host *host = mmc_priv(mmc);
	u32 val;

	val = sdhci_readl(host, INTEL_HS400_ES_REG);
	if (ios->enhanced_strobe)
		val |= INTEL_HS400_ES_BIT;
	else
		val &= ~INTEL_HS400_ES_BIT;
	sdhci_writel(host, val, INTEL_HS400_ES_REG);
}

672
673
static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
					     struct mmc_ios *ios)
674
{
675
676
	struct device *dev = mmc_dev(mmc);
	struct sdhci_host *host = mmc_priv(mmc);
677
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	struct sdhci_pci_slot *slot = sdhci_priv(host);
	struct intel_host *intel_host = sdhci_pci_priv(slot);
679
	unsigned int fn;
680
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	u32 result = 0;
	int err;

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	err = sdhci_start_signal_voltage_switch(mmc, ios);
	if (err)
		return err;

	switch (ios->signal_voltage) {
	case MMC_SIGNAL_VOLTAGE_330:
		fn = INTEL_DSM_V33_SWITCH;
		break;
	case MMC_SIGNAL_VOLTAGE_180:
		fn = INTEL_DSM_V18_SWITCH;
		break;
	default:
		return 0;
	}

	err = intel_dsm(intel_host, dev, fn, &result);
	pr_debug("%s: %s DSM fn %u error %d result %u\n",
		 mmc_hostname(mmc), __func__, fn, err, result);

	return 0;
703
704
}

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static const struct sdhci_ops sdhci_intel_byt_ops = {
	.set_clock		= sdhci_set_clock,
	.set_power		= sdhci_intel_set_power,
	.enable_dma		= sdhci_pci_enable_dma,
709
	.set_bus_width		= sdhci_set_bus_width,
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	.reset			= sdhci_reset,
	.set_uhs_signaling	= sdhci_set_uhs_signaling,
	.hw_reset		= sdhci_pci_hw_reset,
};

715
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static const struct sdhci_ops sdhci_intel_glk_ops = {
	.set_clock		= sdhci_set_clock,
	.set_power		= sdhci_intel_set_power,
	.enable_dma		= sdhci_pci_enable_dma,
	.set_bus_width		= sdhci_set_bus_width,
	.reset			= sdhci_reset,
	.set_uhs_signaling	= sdhci_set_uhs_signaling,
	.hw_reset		= sdhci_pci_hw_reset,
	.irq			= sdhci_cqhci_irq,
};

726
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735
static void byt_read_dsm(struct sdhci_pci_slot *slot)
{
	struct intel_host *intel_host = sdhci_pci_priv(slot);
	struct device *dev = &slot->chip->pdev->dev;
	struct mmc_host *mmc = slot->host->mmc;

	intel_dsm_init(intel_host, dev, mmc);
	slot->chip->rpm_retune = intel_host->d3_retune;
}

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static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
{
	int err = sdhci_execute_tuning(mmc, opcode);
	struct sdhci_host *host = mmc_priv(mmc);

	if (err)
		return err;

	/*
	 * Tuning can leave the IP in an active state (Buffer Read Enable bit
	 * set) which prevents the entry to low power states (i.e. S0i3). Data
	 * reset will clear it.
	 */
	sdhci_reset(host, SDHCI_RESET_DATA);

	return 0;
}

static void byt_probe_slot(struct sdhci_pci_slot *slot)
755
{
756
	struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
757
758
	struct device *dev = &slot->chip->pdev->dev;
	struct mmc_host *mmc = slot->host->mmc;
759

760
	byt_read_dsm(slot);
761

762
763
	byt_ocp_setting(slot->chip->pdev);

764
	ops->execute_tuning = intel_execute_tuning;
765
	ops->start_signal_voltage_switch = intel_start_signal_voltage_switch;
766
767

	device_property_read_u32(dev, "max-frequency", &mmc->f_max);
768
769
770
771
772
}

static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
{
	byt_probe_slot(slot);
773
	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
774
				 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
775
				 MMC_CAP_CMD_DURING_TFR |
776
				 MMC_CAP_WAIT_WHILE_BUSY;
777
	slot->hw_reset = sdhci_pci_int_hw_reset;
778
779
	if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
		slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
780
781
	slot->host->mmc_host_ops.select_drive_strength =
						intel_select_drive_strength;
782
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784
	return 0;
}

785
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788
static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
{
	int ret = byt_emmc_probe_slot(slot);

789
790
	slot->host->mmc->caps2 |= MMC_CAP2_CQE;

791
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794
	if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
		slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
		slot->host->mmc_host_ops.hs400_enhanced_strobe =
						intel_hs400_enhanced_strobe;
795
		slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
796
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798
799
800
	}

	return ret;
}

801
static const struct cqhci_host_ops glk_cqhci_ops = {
802
	.enable		= sdhci_cqe_enable,
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	.disable	= sdhci_cqe_disable,
	.dumpregs	= sdhci_pci_dumpregs,
};

static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
{
	struct device *dev = &slot->chip->pdev->dev;
	struct sdhci_host *host = slot->host;
	struct cqhci_host *cq_host;
	bool dma64;
	int ret;

	ret = sdhci_setup_host(host);
	if (ret)
		return ret;

	cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
	if (!cq_host) {
		ret = -ENOMEM;
		goto cleanup;
	}

	cq_host->mmio = host->ioaddr + 0x200;
	cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
	cq_host->ops = &glk_cqhci_ops;

	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
	if (dma64)
		cq_host->caps |= CQHCI_TASK_DESC_SZ_128;

	ret = cqhci_init(cq_host, host->mmc, dma64);
	if (ret)
		goto cleanup;

	ret = __sdhci_add_host(host);
	if (ret)
		goto cleanup;

	return 0;

cleanup:
	sdhci_cleanup_host(host);
	return ret;
}

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#ifdef CONFIG_PM
#define GLK_RX_CTRL1	0x834
#define GLK_TUN_VAL	0x840
#define GLK_PATH_PLL	GENMASK(13, 8)
#define GLK_DLY		GENMASK(6, 0)
/* Workaround firmware failing to restore the tuning value */
static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp)
{
	struct sdhci_pci_slot *slot = chip->slots[0];
	struct intel_host *intel_host = sdhci_pci_priv(slot);
	struct sdhci_host *host = slot->host;
	u32 glk_rx_ctrl1;
	u32 glk_tun_val;
	u32 dly;

	if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc))
		return;

	glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1);
	glk_tun_val = sdhci_readl(host, GLK_TUN_VAL);

	if (susp) {
		intel_host->glk_rx_ctrl1 = glk_rx_ctrl1;
		intel_host->glk_tun_val = glk_tun_val;
		return;
	}

	if (!intel_host->glk_tun_val)
		return;

	if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) {
		intel_host->rpm_retune_ok = true;
		return;
	}

	dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) +
				  (intel_host->glk_tun_val << 1));
	if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1))
		return;

	glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly;
	sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1);

	intel_host->rpm_retune_ok = true;
	chip->rpm_retune = true;
	mmc_retune_needed(host->mmc);
	pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc));
}

static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp)
{
	if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
	    !chip->rpm_retune)
		glk_rpm_retune_wa(chip, susp);
}

static int glk_runtime_suspend(struct sdhci_pci_chip *chip)
{
	glk_rpm_retune_chk(chip, true);

	return sdhci_cqhci_runtime_suspend(chip);
}

static int glk_runtime_resume(struct sdhci_pci_chip *chip)
{
	glk_rpm_retune_chk(chip, false);

	return sdhci_cqhci_runtime_resume(chip);
}
#endif

919
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936
937
938
939
940
941
942
943
#ifdef CONFIG_ACPI
static int ni_set_max_freq(struct sdhci_pci_slot *slot)
{
	acpi_status status;
	unsigned long long max_freq;

	status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
				       "MXFQ", NULL, &max_freq);
	if (ACPI_FAILURE(status)) {
		dev_err(&slot->chip->pdev->dev,
			"MXFQ not found in acpi table\n");
		return -EINVAL;
	}

	slot->host->mmc->f_max = max_freq * 1000000;

	return 0;
}
#else
static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
{
	return 0;
}
#endif

944
945
static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
{
946
947
	int err;

948
	byt_probe_slot(slot);
949

950
951
952
953
	err = ni_set_max_freq(slot);
	if (err)
		return err;

954
955
956
957
958
	slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
				 MMC_CAP_WAIT_WHILE_BUSY;
	return 0;
}

959
960
static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
{
961
	byt_probe_slot(slot);
962
963
	slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
				 MMC_CAP_WAIT_WHILE_BUSY;
964
965
966
	return 0;
}

967
968
static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
{
969
	byt_probe_slot(slot);
970
	slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
971
				 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
972
973
	slot->cd_idx = 0;
	slot->cd_override_level = true;
974
	if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
975
	    slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
976
	    slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
977
	    slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
978
979
		slot->host->mmc_host_ops.get_cd = bxt_get_cd;

980
981
982
983
	if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI &&
	    slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3)
		slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V;

984
985
986
	return 0;
}

987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
#ifdef CONFIG_PM_SLEEP

static int byt_resume(struct sdhci_pci_chip *chip)
{
	byt_ocp_setting(chip->pdev);

	return sdhci_pci_resume_host(chip);
}

#endif

#ifdef CONFIG_PM

static int byt_runtime_resume(struct sdhci_pci_chip *chip)
{
	byt_ocp_setting(chip->pdev);

	return sdhci_pci_runtime_resume_host(chip);
}

#endif

1009
static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
1010
1011
1012
1013
1014
1015
#ifdef CONFIG_PM_SLEEP
	.resume		= byt_resume,
#endif
#ifdef CONFIG_PM
	.runtime_resume	= byt_runtime_resume,
#endif
1016
1017
	.allow_runtime_pm = true,
	.probe_slot	= byt_emmc_probe_slot,
1018
1019
	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
			  SDHCI_QUIRK_NO_LED,
1020
	.quirks2	= SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1021
			  SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1022
			  SDHCI_QUIRK2_STOP_WITH_TC,
1023
	.ops		= &sdhci_intel_byt_ops,
1024
	.priv_size	= sizeof(struct intel_host),
1025
1026
};

1027
1028
1029
static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
	.allow_runtime_pm	= true,
	.probe_slot		= glk_emmc_probe_slot,
1030
1031
1032
1033
1034
1035
	.add_host		= glk_emmc_add_host,
#ifdef CONFIG_PM_SLEEP
	.suspend		= sdhci_cqhci_suspend,
	.resume			= sdhci_cqhci_resume,
#endif
#ifdef CONFIG_PM
1036
1037
	.runtime_suspend	= glk_runtime_suspend,
	.runtime_resume		= glk_runtime_resume,
1038
#endif
1039
1040
	.quirks			= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
				  SDHCI_QUIRK_NO_LED,
1041
1042
1043
	.quirks2		= SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
				  SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
				  SDHCI_QUIRK2_STOP_WITH_TC,
1044
	.ops			= &sdhci_intel_glk_ops,
1045
1046
1047
	.priv_size		= sizeof(struct intel_host),
};

1048
static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
1049
1050
1051
1052
1053
1054
#ifdef CONFIG_PM_SLEEP
	.resume		= byt_resume,
#endif
#ifdef CONFIG_PM
	.runtime_resume	= byt_runtime_resume,
#endif
1055
1056
	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
			  SDHCI_QUIRK_NO_LED,
1057
1058
1059
1060
1061
	.quirks2	= SDHCI_QUIRK2_HOST_OFF_CARD_ON |
			  SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
	.allow_runtime_pm = true,
	.probe_slot	= ni_byt_sdio_probe_slot,
	.ops		= &sdhci_intel_byt_ops,
1062
	.priv_size	= sizeof(struct intel_host),
1063
1064
};

1065
static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
1066
1067
1068
1069
1070
1071
#ifdef CONFIG_PM_SLEEP
	.resume		= byt_resume,
#endif
#ifdef CONFIG_PM
	.runtime_resume	= byt_runtime_resume,
#endif
1072
1073
	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
			  SDHCI_QUIRK_NO_LED,
1074
1075
	.quirks2	= SDHCI_QUIRK2_HOST_OFF_CARD_ON |
			SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1076
1077
	.allow_runtime_pm = true,
	.probe_slot	= byt_sdio_probe_slot,
1078
	.ops		= &sdhci_intel_byt_ops,
1079
	.priv_size	= sizeof(struct intel_host),
1080
1081
1082
};

static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
1083
1084
1085
1086
1087
1088
#ifdef CONFIG_PM_SLEEP
	.resume		= byt_resume,
#endif
#ifdef CONFIG_PM
	.runtime_resume	= byt_runtime_resume,
#endif
1089
1090
	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
			  SDHCI_QUIRK_NO_LED,
1091
	.quirks2	= SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1092
1093
			  SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
			  SDHCI_QUIRK2_STOP_WITH_TC,
1094
	.allow_runtime_pm = true,
1095
	.own_cd_for_runtime_pm = true,
1096
	.probe_slot	= byt_sd_probe_slot,
1097
	.ops		= &sdhci_intel_byt_ops,
1098
	.priv_size	= sizeof(struct intel_host),
1099
1100
};

1101
/* Define Host controllers for Intel Merrifield platform */
1102
1103
#define INTEL_MRFLD_EMMC_0	0
#define INTEL_MRFLD_EMMC_1	1
1104
#define INTEL_MRFLD_SD		2
1105
#define INTEL_MRFLD_SDIO	3
1106

1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
#ifdef CONFIG_ACPI
static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
{
	struct acpi_device *device, *child;

	device = ACPI_COMPANION(&slot->chip->pdev->dev);
	if (!device)
		return;

	acpi_device_fix_up_power(device);
	list_for_each_entry(child, &device->children, node)
		if (child->status.present && child->status.enabled)
			acpi_device_fix_up_power(child);
}
#else
static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
#endif

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static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
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{
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	unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);

	switch (func) {
	case INTEL_MRFLD_EMMC_0:
	case INTEL_MRFLD_EMMC_1:
		slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
					 MMC_CAP_8_BIT_DATA |
					 MMC_CAP_1_8V_DDR;
		break;
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	case INTEL_MRFLD_SD:
		slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
		break;
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	case INTEL_MRFLD_SDIO:
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		/* Advertise 2.0v for compatibility with the SDIO card's OCR */
		slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
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		slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
					 MMC_CAP_POWER_OFF_CARD;
		break;
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	default:
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		return -ENODEV;
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	}
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	intel_mrfld_mmc_fix_up_power_slot(slot);
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	return 0;
}

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static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
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	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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	.quirks2	= SDHCI_QUIRK2_BROKEN_HS200 |
			SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
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	.allow_runtime_pm = true,
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	.probe_slot	= intel_mrfld_mmc_probe_slot,
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};

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static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
{
	u8 scratch;
	int ret;

	ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
	if (ret)
		return ret;

	/*
	 * Turn PMOS on [bit 0], set over current detection to 2.4 V
	 * [bit 1:2] and enable over current debouncing [bit 6].
	 */
	if (on)
		scratch |= 0x47;
	else
		scratch &= ~0x47;

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	return pci_write_config_byte(chip->pdev, 0xAE, scratch);
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}

static int jmicron_probe(struct sdhci_pci_chip *chip)
{
	int ret;
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	u16 mmcdev = 0;
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	if (chip->pdev->revision == 0) {
		chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
			  SDHCI_QUIRK_32BIT_DMA_SIZE |
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			  SDHCI_QUIRK_32BIT_ADMA_SIZE |
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			  SDHCI_QUIRK_RESET_AFTER_REQUEST |
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			  SDHCI_QUIRK_BROKEN_SMALL_PIO;
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	}

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	/*
	 * JMicron chips can have two interfaces to the same hardware
	 * in order to work around limitations in Microsoft's driver.
	 * We need to make sure we only bind to one of them.
	 *
	 * This code assumes two things:
	 *
	 * 1. The PCI code adds subfunctions in order.
	 *
	 * 2. The MMC interface has a lower subfunction number
	 *    than the SD interface.
	 */
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	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
		mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
	else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
		mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;

	if (mmcdev) {
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		struct pci_dev *sd_dev;

		sd_dev = NULL;
		while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
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						mmcdev, sd_dev)) != NULL) {
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			if ((PCI_SLOT(chip->pdev->devfn) ==
				PCI_SLOT(sd_dev->devfn)) &&
				(chip->pdev->bus == sd_dev->bus))
				break;
		}

		if (sd_dev) {
			pci_dev_put(sd_dev);
			dev_info(&chip->pdev->dev, "Refusing to bind to "
				"secondary interface.\n");
			return -ENODEV;
		}
	}

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	/*
	 * JMicron chips need a bit of a nudge to enable the power
	 * output pins.
	 */
	ret = jmicron_pmos(chip, 1);
	if (ret) {
		dev_err(&chip->pdev->dev, "Failure enabling card power\n");
		return ret;
	}

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	/* quirk for unsable RO-detection on JM388 chips */
	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
	    chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
		chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;

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	return 0;
}

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static void jmicron_enable_mmc(struct sdhci_host *host, int on)
{
	u8 scratch;

	scratch = readb(host->ioaddr + 0xC0);

	if (on)
		scratch |= 0x01;
	else
		scratch &= ~0x01;

	writeb(scratch, host->ioaddr + 0xC0);
}

static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
{
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	if (slot->chip->pdev->revision == 0) {
		u16 version;

		version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
		version = (version & SDHCI_VENDOR_VER_MASK) >>
			SDHCI_VENDOR_VER_SHIFT;

		/*
		 * Older versions of the chip have lots of nasty glitches
		 * in the ADMA engine. It's best just to avoid it
		 * completely.
		 */
		if (version < 0xAC)
			slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
	}

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	/* JM388 MMC doesn't support 1.8V while SD supports it */
	if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
		slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
			MMC_VDD_29_30 | MMC_VDD_30_31 |
			MMC_VDD_165_195; /* allow 1.8V */
		slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
			MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
	}

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	/*
	 * The secondary interface requires a bit set to get the
	 * interrupts.
	 */
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	if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
	    slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
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		jmicron_enable_mmc(slot->host, 1);

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	slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;

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	return 0;
}

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Pierre Ossman committed
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static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
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{
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	if (dead)
		return;

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	if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
	    slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
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		jmicron_enable_mmc(slot->host, 0);
}

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#ifdef CONFIG_PM_SLEEP
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static int jmicron_suspend(struct sdhci_pci_chip *chip)
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{
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	int i, ret;

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	ret = sdhci_pci_suspend_host(chip);
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	if (ret)
		return ret;
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	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
	    chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
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		for (i = 0; i < chip->num_slots; i++)
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			jmicron_enable_mmc(chip->slots[i]->host, 0);
	}

	return 0;
}

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static int jmicron_resume(struct sdhci_pci_chip *chip)
{
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	int ret, i;

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	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
	    chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
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		for (i = 0; i < chip->num_slots; i++)
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			jmicron_enable_mmc(chip->slots[i]->host, 1);
	}
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	ret = jmicron_pmos(chip, 1);
	if (ret) {
		dev_err(&chip->pdev->dev, "Failure enabling card power\n");
		return ret;
	}

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	return sdhci_pci_resume_host(chip);
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}
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#endif
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static const struct sdhci_pci_fixes sdhci_jmicron = {
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	.probe		= jmicron_probe,

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	.probe_slot	= jmicron_probe_slot,
	.remove_slot	= jmicron_remove_slot,