• Andrew Jeffery's avatar
    mmc: sdhci-of-aspeed: Add support for the ASPEED SD controller · bb7b8ec6
    Andrew Jeffery authored
    Add a minimal driver for ASPEED's SD controller, which exposes two
    The ASPEED design implements a common register set for the SDHCIs, and
    moves some of the standard configuration elements out to this common
    area (e.g. 8-bit mode, and card detect configuration which is not
    currently supported).
    The SD controller has a dedicated hardware interrupt that is shared
    between the slots. The common register set exposes information on which
    slot triggered the interrupt; early revisions of the patch introduced an
    irqchip for the register, but reality is it doesn't behave as an
    irqchip, and the result fits awkwardly into the irqchip APIs. Instead
    I've taken the simple approach of using the IRQ as a shared IRQ with
    some minor performance impact for the second slot.
    Ryan was the original author of the patch - I've taken his work and
    massaged it to drop the irqchip support and rework the devicetree
    integration. The driver has been smoke tested under qemu against a
    minimal SD controller model and lightly tested on an ast2500-evb.
    Signed-off-by: default avatarRyan Chen <ryanchen.aspeed@gmail.com>
    Signed-off-by: default avatarAndrew Jeffery <andrew@aj.id.au>
    Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
    Reviewed-by: default avatarJoel Stanley <joel@jms.id.au>
    Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>