Unverified Commit 94f592f0 authored by Zong Li's avatar Zong Li Committed by Palmer Dabbelt
Browse files

RISC-V: Add the directive for alignment of stvec's value

The stvec's value must be 4 byte alignment by specification definition.
These directives avoid to stvec be set the non-alignment value.

Signed-off-by: default avatarZong Li <zong@andestech.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 62b01943
......@@ -94,6 +94,7 @@ relocate:
or a0, a0, a1
csrw sptbr, a0
.align 2
/* Set trap vector to spin forever to help debug */
la a0, .Lsecondary_park
......@@ -143,6 +144,7 @@ relocate:
tail smp_callin
.align 2
/* We lack SMP support or have too many harts, so park this hart */
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