Commit d4fd0404 authored by Claudiu Manoil's avatar Claudiu Manoil Committed by David S. Miller
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enetc: Introduce basic PF and VF ENETC ethernet drivers



ENETC is a multi-port virtualized Ethernet controller supporting GbE
designs and Time-Sensitive Networking (TSN) functionality.
ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
Endpoint (RCIE).  As such, it contains multiple physical (PF) and
virtual (VF) PCIe functions, discoverable by standard PCI Express.

Introduce basic PF and VF ENETC ethernet drivers.  The PF has access to
the ENETC Port registers and resources and makes the required privileged
configurations for the underlying VF devices.  Common functionality is
controlled through so called System Interface (SI) register blocks, PFs
and VFs own a SI each.  Though SI register blocks are almost identical,
there are a few privileged SI level controls that are accessible only to
PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
As such, the bulk of the code, including datapath processing, basic h/w
offload support and generic pci related configuration, is shared between
the 2 drivers and is factored out in common source files (i.e. enetc.c).

Major functionalities included (for both drivers):
MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
CTAG filtering, VF mac address config support, VF VLAN isolation support,
etc.

Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 5e5b9f62
......@@ -6023,6 +6023,12 @@ L: linuxppc-dev@lists.ozlabs.org
S: Maintained
F: drivers/dma/fsldma.*
FREESCALE ENETC ETHERNET DRIVERS
M: Claudiu Manoil <claudiu.manoil@nxp.com>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ethernet/freescale/enetc/
FREESCALE eTSEC ETHERNET DRIVER (GIANFAR)
M: Claudiu Manoil <claudiu.manoil@nxp.com>
L: netdev@vger.kernel.org
......
......@@ -97,5 +97,6 @@ config GIANFAR
source "drivers/net/ethernet/freescale/dpaa/Kconfig"
source "drivers/net/ethernet/freescale/dpaa2/Kconfig"
source "drivers/net/ethernet/freescale/enetc/Kconfig"
endif # NET_VENDOR_FREESCALE
......@@ -23,3 +23,6 @@ obj-$(CONFIG_FSL_FMAN) += fman/
obj-$(CONFIG_FSL_DPAA_ETH) += dpaa/
obj-$(CONFIG_FSL_DPAA2_ETH) += dpaa2/
obj-$(CONFIG_FSL_ENETC) += enetc/
obj-$(CONFIG_FSL_ENETC_VF) += enetc/
# SPDX-License-Identifier: GPL-2.0
config FSL_ENETC
tristate "ENETC PF driver"
depends on PCI && PCI_MSI && (ARCH_LAYERSCAPE || COMPILE_TEST)
help
This driver supports NXP ENETC gigabit ethernet controller PCIe
physical function (PF) devices, managing ENETC Ports at a privileged
level.
If compiled as module (M), the module name is fsl-enetc.
config FSL_ENETC_VF
tristate "ENETC VF driver"
depends on PCI && PCI_MSI && (ARCH_LAYERSCAPE || COMPILE_TEST)
help
This driver supports NXP ENETC gigabit ethernet controller PCIe
virtual function (VF) devices enabled by the ENETC PF driver.
If compiled as module (M), the module name is fsl-enetc-vf.
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_FSL_ENETC) += fsl-enetc.o
fsl-enetc-$(CONFIG_FSL_ENETC) += enetc.o enetc_cbdr.o enetc_ethtool.o
fsl-enetc-objs := enetc_pf.o $(fsl-enetc-y)
obj-$(CONFIG_FSL_ENETC_VF) += fsl-enetc-vf.o
ifeq ($(CONFIG_FSL_ENETC)$(CONFIG_FSL_ENETC_VF), yy)
fsl-enetc-vf-objs := enetc_vf.o
else
fsl-enetc-vf-$(CONFIG_FSL_ENETC_VF) += enetc.o enetc_cbdr.o \
enetc_ethtool.o
fsl-enetc-vf-objs := enetc_vf.o $(fsl-enetc-vf-y)
endif
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/* Copyright 2017-2019 NXP */
#include <linux/timer.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/dma-mapping.h>
#include <linux/skbuff.h>
#include <linux/ethtool.h>
#include <linux/if_vlan.h>
#include <linux/phy.h>
#include "enetc_hw.h"
#define ENETC_MAC_MAXFRM_SIZE 9600
#define ENETC_MAX_MTU (ENETC_MAC_MAXFRM_SIZE - \
(ETH_FCS_LEN + ETH_HLEN + VLAN_HLEN))
struct enetc_tx_swbd {
struct sk_buff *skb;
dma_addr_t dma;
u16 len;
u16 is_dma_page;
};
#define ENETC_RX_MAXFRM_SIZE ENETC_MAC_MAXFRM_SIZE
#define ENETC_RXB_TRUESIZE 2048 /* PAGE_SIZE >> 1 */
#define ENETC_RXB_PAD NET_SKB_PAD /* add extra space if needed */
#define ENETC_RXB_DMA_SIZE \
(SKB_WITH_OVERHEAD(ENETC_RXB_TRUESIZE) - ENETC_RXB_PAD)
struct enetc_rx_swbd {
dma_addr_t dma;
struct page *page;
u16 page_offset;
};
struct enetc_ring_stats {
unsigned int packets;
unsigned int bytes;
unsigned int rx_alloc_errs;
};
#define ENETC_BDR_DEFAULT_SIZE 1024
#define ENETC_DEFAULT_TX_WORK 256
struct enetc_bdr {
struct device *dev; /* for DMA mapping */
struct net_device *ndev;
void *bd_base; /* points to Rx or Tx BD ring */
union {
void __iomem *tpir;
void __iomem *rcir;
};
u16 index;
int bd_count; /* # of BDs */
int next_to_use;
int next_to_clean;
union {
struct enetc_tx_swbd *tx_swbd;
struct enetc_rx_swbd *rx_swbd;
};
union {
void __iomem *tcir; /* Tx */
int next_to_alloc; /* Rx */
};
void __iomem *idr; /* Interrupt Detect Register pointer */
struct enetc_ring_stats stats;
dma_addr_t bd_dma_base;
} ____cacheline_aligned_in_smp;
static inline void enetc_bdr_idx_inc(struct enetc_bdr *bdr, int *i)
{
if (unlikely(++*i == bdr->bd_count))
*i = 0;
}
static inline int enetc_bd_unused(struct enetc_bdr *bdr)
{
if (bdr->next_to_clean > bdr->next_to_use)
return bdr->next_to_clean - bdr->next_to_use - 1;
return bdr->bd_count + bdr->next_to_clean - bdr->next_to_use - 1;
}
/* Control BD ring */
#define ENETC_CBDR_DEFAULT_SIZE 64
struct enetc_cbdr {
void *bd_base; /* points to Rx or Tx BD ring */
void __iomem *pir;
void __iomem *cir;
int bd_count; /* # of BDs */
int next_to_use;
int next_to_clean;
dma_addr_t bd_dma_base;
};
#define ENETC_TXBD(BDR, i) (&(((union enetc_tx_bd *)((BDR).bd_base))[i]))
#define ENETC_RXBD(BDR, i) (&(((union enetc_rx_bd *)((BDR).bd_base))[i]))
#define ENETC_REV1 0x1
enum enetc_errata {
ENETC_ERR_TXCSUM = BIT(0),
ENETC_ERR_VLAN_ISOL = BIT(1),
ENETC_ERR_UCMCSWP = BIT(2),
};
/* PCI IEP device data */
struct enetc_si {
struct pci_dev *pdev;
struct enetc_hw hw;
enum enetc_errata errata;
struct net_device *ndev; /* back ref. */
struct enetc_cbdr cbd_ring;
int num_rx_rings; /* how many rings are available in the SI */
int num_tx_rings;
unsigned short pad;
};
#define ENETC_SI_ALIGN 32
static inline void *enetc_si_priv(const struct enetc_si *si)
{
return (char *)si + ALIGN(sizeof(struct enetc_si), ENETC_SI_ALIGN);
}
static inline bool enetc_si_is_pf(struct enetc_si *si)
{
return !!(si->hw.port);
}
#define ENETC_MAX_NUM_TXQS 8
#define ENETC_INT_NAME_MAX (IFNAMSIZ + 8)
struct enetc_int_vector {
void __iomem *rbier;
void __iomem *tbier_base;
unsigned long tx_rings_map;
int count_tx_rings;
struct napi_struct napi;
char name[ENETC_INT_NAME_MAX];
struct enetc_bdr rx_ring ____cacheline_aligned_in_smp;
struct enetc_bdr tx_ring[0];
};
#define ENETC_MAX_BDR_INT 2 /* fixed to max # of available cpus */
struct enetc_ndev_priv {
struct net_device *ndev;
struct device *dev; /* dma-mapping device */
struct enetc_si *si;
int bdr_int_num; /* number of Rx/Tx ring interrupts */
struct enetc_int_vector *int_vector[ENETC_MAX_BDR_INT];
u16 num_rx_rings, num_tx_rings;
u16 rx_bd_count, tx_bd_count;
u16 msg_enable;
struct enetc_bdr *tx_ring[16];
struct enetc_bdr *rx_ring[16];
struct device_node *phy_node;
phy_interface_t if_mode;
};
#define ENETC_CBD(R, i) (&(((struct enetc_cbd *)((R).bd_base))[i]))
#define ENETC_CBDR_TIMEOUT 1000 /* usecs */
/* SI common */
int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv);
void enetc_pci_remove(struct pci_dev *pdev);
int enetc_alloc_msix(struct enetc_ndev_priv *priv);
void enetc_free_msix(struct enetc_ndev_priv *priv);
void enetc_get_si_caps(struct enetc_si *si);
void enetc_init_si_rings_params(struct enetc_ndev_priv *priv);
int enetc_alloc_si_resources(struct enetc_ndev_priv *priv);
void enetc_free_si_resources(struct enetc_ndev_priv *priv);
int enetc_open(struct net_device *ndev);
int enetc_close(struct net_device *ndev);
netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev);
struct net_device_stats *enetc_get_stats(struct net_device *ndev);
/* ethtool */
void enetc_set_ethtool_ops(struct net_device *ndev);
/* control buffer descriptor ring (CBDR) */
int enetc_set_mac_flt_entry(struct enetc_si *si, int index,
char *mac_addr, int si_map);
int enetc_clear_mac_flt_entry(struct enetc_si *si, int index);
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/* Copyright 2017-2019 NXP */
#include "enetc.h"
static void enetc_clean_cbdr(struct enetc_si *si)
{
struct enetc_cbdr *ring = &si->cbd_ring;
struct enetc_cbd *dest_cbd;
int i, status;
i = ring->next_to_clean;
while (enetc_rd_reg(ring->cir) != i) {
dest_cbd = ENETC_CBD(*ring, i);
status = dest_cbd->status_flags & ENETC_CBD_STATUS_MASK;
if (status)
dev_warn(&si->pdev->dev, "CMD err %04x for cmd %04x\n",
status, dest_cbd->cmd);
memset(dest_cbd, 0, sizeof(*dest_cbd));
i = (i + 1) % ring->bd_count;
}
ring->next_to_clean = i;
}
static int enetc_cbd_unused(struct enetc_cbdr *r)
{
return (r->next_to_clean - r->next_to_use - 1 + r->bd_count) %
r->bd_count;
}
static int enetc_send_cmd(struct enetc_si *si, struct enetc_cbd *cbd)
{
struct enetc_cbdr *ring = &si->cbd_ring;
int timeout = ENETC_CBDR_TIMEOUT;
struct enetc_cbd *dest_cbd;
int i;
if (unlikely(!ring->bd_base))
return -EIO;
if (unlikely(!enetc_cbd_unused(ring)))
enetc_clean_cbdr(si);
i = ring->next_to_use;
dest_cbd = ENETC_CBD(*ring, i);
/* copy command to the ring */
*dest_cbd = *cbd;
i = (i + 1) % ring->bd_count;
ring->next_to_use = i;
/* let H/W know BD ring has been updated */
enetc_wr_reg(ring->pir, i);
do {
if (enetc_rd_reg(ring->cir) == i)
break;
udelay(10); /* cannot sleep, rtnl_lock() */
timeout -= 10;
} while (timeout);
if (!timeout)
return -EBUSY;
enetc_clean_cbdr(si);
return 0;
}
int enetc_clear_mac_flt_entry(struct enetc_si *si, int index)
{
struct enetc_cbd cbd;
memset(&cbd, 0, sizeof(cbd));
cbd.cls = 1;
cbd.status_flags = ENETC_CBD_FLAGS_SF;
cbd.index = cpu_to_le16(index);
return enetc_send_cmd(si, &cbd);
}
int enetc_set_mac_flt_entry(struct enetc_si *si, int index,
char *mac_addr, int si_map)
{
struct enetc_cbd cbd;
u32 upper;
u16 lower;
memset(&cbd, 0, sizeof(cbd));
/* fill up the "set" descriptor */
cbd.cls = 1;
cbd.status_flags = ENETC_CBD_FLAGS_SF;
cbd.index = cpu_to_le16(index);
cbd.opt[3] = cpu_to_le32(si_map);
/* enable entry */
cbd.opt[0] = cpu_to_le32(BIT(31));
upper = *(const u32 *)mac_addr;
lower = *(const u16 *)(mac_addr + 4);
cbd.addr[0] = cpu_to_le32(upper);
cbd.addr[1] = cpu_to_le32(lower);
return enetc_send_cmd(si, &cbd);
}
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/* Copyright 2017-2019 NXP */
#include <linux/net_tstamp.h>
#include <linux/module.h>
#include "enetc.h"
static const u32 enetc_si_regs[] = {
ENETC_SIMR, ENETC_SIPMAR0, ENETC_SIPMAR1, ENETC_SICBDRMR,
ENETC_SICBDRSR, ENETC_SICBDRBAR0, ENETC_SICBDRBAR1, ENETC_SICBDRPIR,
ENETC_SICBDRCIR, ENETC_SICBDRLENR, ENETC_SICAPR0, ENETC_SICAPR1,
ENETC_SIUEFDCR
};
static const u32 enetc_txbdr_regs[] = {
ENETC_TBMR, ENETC_TBSR, ENETC_TBBAR0, ENETC_TBBAR1,
ENETC_TBPIR, ENETC_TBCIR, ENETC_TBLENR, ENETC_TBIER
};
static const u32 enetc_rxbdr_regs[] = {
ENETC_RBMR, ENETC_RBSR, ENETC_RBBSR, ENETC_RBCIR, ENETC_RBBAR0,
ENETC_RBBAR1, ENETC_RBPIR, ENETC_RBLENR, ENETC_RBICIR0, ENETC_RBIER
};
static const u32 enetc_port_regs[] = {
ENETC_PMR, ENETC_PSR, ENETC_PSIPMR, ENETC_PSIPMAR0(0),
ENETC_PSIPMAR1(0), ENETC_PTXMBAR, ENETC_PCAPR0, ENETC_PCAPR1,
ENETC_PSICFGR0(0), ENETC_PTCMSDUR(0), ENETC_PM0_CMD_CFG,
ENETC_PM0_MAXFRM, ENETC_PM0_IF_MODE
};
static int enetc_get_reglen(struct net_device *ndev)
{
struct enetc_ndev_priv *priv = netdev_priv(ndev);
struct enetc_hw *hw = &priv->si->hw;
int len;
len = ARRAY_SIZE(enetc_si_regs);
len += ARRAY_SIZE(enetc_txbdr_regs) * priv->num_tx_rings;
len += ARRAY_SIZE(enetc_rxbdr_regs) * priv->num_rx_rings;
if (hw->port)
len += ARRAY_SIZE(enetc_port_regs);
len *= sizeof(u32) * 2; /* store 2 entries per reg: addr and value */
return len;
}
static void enetc_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
void *regbuf)
{
struct enetc_ndev_priv *priv = netdev_priv(ndev);
struct enetc_hw *hw = &priv->si->hw;
u32 *buf = (u32 *)regbuf;
int i, j;
u32 addr;
for (i = 0; i < ARRAY_SIZE(enetc_si_regs); i++) {
*buf++ = enetc_si_regs[i];
*buf++ = enetc_rd(hw, enetc_si_regs[i]);
}
for (i = 0; i < priv->num_tx_rings; i++) {
for (j = 0; j < ARRAY_SIZE(enetc_txbdr_regs); j++) {
addr = ENETC_BDR(TX, i, enetc_txbdr_regs[j]);
*buf++ = addr;
*buf++ = enetc_rd(hw, addr);
}
}
for (i = 0; i < priv->num_rx_rings; i++) {
for (j = 0; j < ARRAY_SIZE(enetc_rxbdr_regs); j++) {
addr = ENETC_BDR(RX, i, enetc_rxbdr_regs[j]);
*buf++ = addr;
*buf++ = enetc_rd(hw, addr);
}
}
if (!hw->port)
return;
for (i = 0; i < ARRAY_SIZE(enetc_port_regs); i++) {
addr = ENETC_PORT_BASE + enetc_port_regs[i];
*buf++ = addr;
*buf++ = enetc_rd(hw, addr);
}
}
static void enetc_get_ringparam(struct net_device *ndev,
struct ethtool_ringparam *ring)
{
struct enetc_ndev_priv *priv = netdev_priv(ndev);
ring->rx_pending = priv->rx_bd_count;
ring->tx_pending = priv->tx_bd_count;
/* do some h/w sanity checks for BDR length */
if (netif_running(ndev)) {
struct enetc_hw *hw = &priv->si->hw;
u32 val = enetc_rxbdr_rd(hw, 0, ENETC_RBLENR);
if (val != priv->rx_bd_count)
netif_err(priv, hw, ndev, "RxBDR[RBLENR] = %d!\n", val);
val = enetc_txbdr_rd(hw, 0, ENETC_TBLENR);
if (val != priv->tx_bd_count)
netif_err(priv, hw, ndev, "TxBDR[TBLENR] = %d!\n", val);
}
}
static const struct ethtool_ops enetc_pf_ethtool_ops = {
.get_regs_len = enetc_get_reglen,
.get_regs = enetc_get_regs,
.get_ringparam = enetc_get_ringparam,
.get_link_ksettings = phy_ethtool_get_link_ksettings,
.set_link_ksettings = phy_ethtool_set_link_ksettings,
};
static const struct ethtool_ops enetc_vf_ethtool_ops = {
.get_regs_len = enetc_get_reglen,
.get_regs = enetc_get_regs,
.get_ringparam = enetc_get_ringparam,
};
void enetc_set_ethtool_ops(struct net_device *ndev)
{
struct enetc_ndev_priv *priv = netdev_priv(ndev);
if (enetc_si_is_pf(priv->si))
ndev->ethtool_ops = &enetc_pf_ethtool_ops;
else
ndev->ethtool_ops = &enetc_vf_ethtool_ops;
}
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/* Copyright 2017-2019 NXP */
#include <linux/bitops.h>
/* ENETC device IDs */
#define ENETC_DEV_ID_PF 0xe100
#define ENETC_DEV_ID_VF 0xef00
/* ENETC register block BAR */
#define ENETC_BAR_REGS 0
/** SI regs, offset: 0h */
#define ENETC_SIMR 0
#define ENETC_SIMR_EN BIT(31)
#define ENETC_SICTR0 0x18
#define ENETC_SICTR1 0x1c
#define ENETC_SIPCAPR0 0x20
#define ENETC_SIPCAPR1 0x24
#define ENETC_SITGTGR 0x30
#define ENETC_SIRBGCR 0x38
/* cache attribute registers for transactions initiated by ENETC */
#define ENETC_SICAR0 0x40
#define ENETC_SICAR1 0x44
#define ENETC_SICAR2 0x48
/* rd snoop, no alloc
* wr snoop, no alloc, partial cache line update for BDs and full cache line
* update for data
*/
#define ENETC_SICAR_RD_COHERENT 0x2b2b0000
#define ENETC_SICAR_WR_COHERENT 0x00006727
#define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */
#define ENETC_SIPMAR0 0x80
#define ENETC_SIPMAR1 0x84
/* Control BDR regs */
#define ENETC_SICBDRMR 0x800
#define ENETC_SICBDRSR 0x804 /* RO */
#define ENETC_SICBDRBAR0 0x810
#define ENETC_SICBDRBAR1 0x814
#define ENETC_SICBDRPIR 0x818
#define ENETC_SICBDRCIR 0x81c
#define ENETC_SICBDRLENR 0x820
#define ENETC_SICAPR0 0x900
#define ENETC_SICAPR1 0x904
#define ENETC_PSIIER 0xa00
#define ENETC_PSIIER_MR_MASK GENMASK(2, 1)
#define ENETC_PSIIDR 0xa08
#define ENETC_SITXIDR 0xa18
#define ENETC_SIRXIDR 0xa28
#define ENETC_SIMSIVR 0xa30
#define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4)
#define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4)
#define ENETC_SIUEFDCR 0xe28
/** SI BDR sub-blocks, n = 0..7 */
enum enetc_bdr_type {TX, RX};
#define ENETC_BDR_OFF(i) ((i) * 0x200)
#define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r))
/* RX BDR reg offsets */
#define ENETC_RBMR 0
#define ENETC_RBMR_BDS BIT(2)
#define ENETC_RBMR_VTE BIT(5)
#define ENETC_RBMR_EN BIT(31)
#define ENETC_RBSR 0x4
#define ENETC_RBBSR 0x8
#define ENETC_RBCIR 0xc
#define ENETC_RBBAR0 0x10
#define ENETC_RBBAR1 0x14
#define ENETC_RBPIR 0x18
#define ENETC_RBLENR 0x20
#define ENETC_RBIER 0xa0
#define ENETC_RBIER_RXTIE BIT(0)
#define ENETC_RBIDR 0xa4
#define ENETC_RBICIR0 0xa8
#define ENETC_RBICIR0_ICEN BIT(31)
/* TX BDR reg offsets */
#define ENETC_TBMR 0
#define ENETC_TBSR_BUSY BIT(0)