1. 22 Sep, 2019 1 commit
    • Mao Wenan's avatar
      net: dsa: sja1105: Add dependency for NET_DSA_SJA1105_TAS · a8d570de
      Mao Wenan authored
      If CONFIG_NET_DSA_SJA1105_TAS=y and CONFIG_NET_SCH_TAPRIO=n,
      below error can be found:
      drivers/net/dsa/sja1105/sja1105_tas.o: In function `sja1105_setup_tc_taprio':
      sja1105_tas.c:(.text+0x318): undefined reference to `taprio_offload_free'
      sja1105_tas.c:(.text+0x590): undefined reference to `taprio_offload_get'
      drivers/net/dsa/sja1105/sja1105_tas.o: In function `sja1105_tas_teardown':
      sja1105_tas.c:(.text+0x610): undefined reference to `taprio_offload_free'
      make: *** [vmlinux] Error 1
      
      sja1105_tas needs tc-taprio, so this patch add the dependency for it.
      
      Fixes: 317ab5b8
      
       ("net: dsa: sja1105: Configure the Time-Aware Scheduler via tc-taprio offload")
      Signed-off-by: default avatarMao Wenan <maowenan@huawei.com>
      Reviewed-by: default avatarVladimir Oltean <olteanv@gmail.com>
      Signed-off-by: default avatarJakub Kicinski <jakub.kicinski@netronome.com>
      a8d570de
  2. 16 Sep, 2019 1 commit
    • Vladimir Oltean's avatar
      net: dsa: sja1105: Configure the Time-Aware Scheduler via tc-taprio offload · 317ab5b8
      Vladimir Oltean authored
      
      
      This qdisc offload is the closest thing to what the SJA1105 supports in
      hardware for time-based egress shaping. The switch core really is built
      around SAE AS6802/TTEthernet (a TTTech standard) but can be made to
      operate similarly to IEEE 802.1Qbv with some constraints:
      
      - The gate control list is a global list for all ports. There are 8
        execution threads that iterate through this global list in parallel.
        I don't know why 8, there are only 4 front-panel ports.
      
      - Care must be taken by the user to make sure that two execution threads
        never get to execute a GCL entry simultaneously. I created a O(n^4)
        checker for this hardware limitation, prior to accepting a taprio
        offload configuration as valid.
      
      - The spec says that if a GCL entry's interval is shorter than the frame
        length, you shouldn't send it (and end up in head-of-line blocking).
        Well, this switch does anyway.
      
      - The switch has no concept of ADMIN and OPER configurations. Because
        it's so simple, the TAS settings are loaded through the static config
        tables interface, so there isn't even place for any discussion about
        'graceful switchover between ADMIN and OPER'. You just reset the
        switch and upload a new OPER config.
      
      - The switch accepts multiple time sources for the gate events. Right
        now I am using the standalone clock source as opposed to PTP. So the
        base time parameter doesn't really do much. Support for the PTP clock
        source will be added in a future series.
      Signed-off-by: default avatarVladimir Oltean <olteanv@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      317ab5b8
  3. 17 Jun, 2019 1 commit
    • Arnd Bergmann's avatar
      net: dsa: sja1105: fix ptp link error · 78fe8a28
      Arnd Bergmann authored
      Due to a reversed dependency, it is possible to build
      the lower ptp driver as a loadable module and the actual
      driver using it as built-in, causing a link error:
      
      drivers/net/dsa/sja1105/sja1105_spi.o: In function `sja1105_static_config_upload':
      sja1105_spi.c:(.text+0x6f0): undefined reference to `sja1105_ptp_reset'
      drivers/net/dsa/sja1105/sja1105_spi.o:(.data+0x2d4): undefined reference to `sja1105et_ptp_cmd'
      drivers/net/dsa/sja1105/sja1105_spi.o:(.data+0x604): undefined reference to `sja1105pqrs_ptp_cmd'
      drivers/net/dsa/sja1105/sja1105_main.o: In function `sja1105_remove':
      sja1105_main.c:(.text+0x8d4): undefined reference to `sja1105_ptp_clock_unregister'
      drivers/net/dsa/sja1105/sja1105_main.o: In function `sja1105_rxtstamp_work':
      sja1105_main.c:(.text+0x964): undefined reference to `sja1105_tstamp_reconstruct'
      drivers/net/dsa/sja1105/sja1105_main.o: In function `sja1105_setup':
      sja1105_main.c:(.text+0xb7c): undefined reference to `sja1105_ptp_clock_register'
      drivers/net/dsa/sja1105/sja1105_main.o: In function `sja1105_port_deferred_xmit':
      sja1105_main.c:(.text+0x1fa0): undefined reference to `sja1105_ptpegr_ts_poll'
      sja1105_main.c:(.text+0x1fc4): undefined reference to `sja1105_tstamp_reconstruct'
      drivers/net/dsa/sja1105/sja1105_main.o:(.rodata+0x5b0): undefined reference to `sja1105_get_ts_info'
      
      Change the Makefile logic to always build the ptp module
      the same way as the rest. Another option would be to
      just add it to the same module and remove the exports,
      but I don't know if there was a good reason to keep them
      separate.
      
      Fixes: bb77f36a
      
       ("net: dsa: sja1105: Add support for the PTP clock")
      Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      78fe8a28
  4. 10 Jun, 2019 1 commit
  5. 08 Jun, 2019 1 commit
    • Vladimir Oltean's avatar
      net: dsa: sja1105: Add support for the PTP clock · bb77f36a
      Vladimir Oltean authored
      
      
      The design of this PHC driver is influenced by the switch's behavior
      w.r.t. timestamping.  It exposes two PTP counters, one free-running
      (PTPTSCLK) and the other offset- and frequency-corrected in hardware
      through PTPCLKVAL, PTPCLKADD and PTPCLKRATE.  The MACs can sample either
      of these for frame timestamps.
      
      However, the user manual warns that taking timestamps based on the
      corrected clock is less than useful, as the switch can deliver corrupted
      timestamps in a variety of circumstances.
      
      Therefore, this PHC uses the free-running PTPTSCLK together with a
      timecounter/cyclecounter structure that translates it into a software
      time domain.  Thus, the settime/adjtime and adjfine callbacks are
      hardware no-ops.
      
      The timestamps (introduced in a further patch) will also be translated
      to the correct time domain before being handed over to the userspace PTP
      stack.
      
      The introduction of a second set of PHC operations that operate on the
      hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat
      unavoidable, as the TTEthernet core uses the corrected PTP time domain.
      However, the free-running counter + timecounter structure combination
      will suffice for now, as the resulting timestamps yield a sub-50 ns
      synchronization offset in steady state using linuxptp.
      
      For this patch, in absence of frame timestamping, the operations of the
      switch PHC were tested by syncing it to the system time as a local slave
      clock with:
      
      phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01
      Signed-off-by: default avatarVladimir Oltean <olteanv@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      bb77f36a
  6. 21 May, 2019 1 commit
  7. 06 May, 2019 1 commit
    • Vladimir Oltean's avatar
      net: dsa: sja1105: Add support for traffic through standalone ports · 227d07a0
      Vladimir Oltean authored
      
      
      In order to support this, we are creating a make-shift switch tag out of
      a VLAN trunk configured on the CPU port. Termination of normal traffic
      on switch ports only works when not under a vlan_filtering bridge.
      Termination of management (PTP, BPDU) traffic works under all
      circumstances because it uses a different tagging mechanism
      (incl_srcpt). We are making use of the generic CONFIG_NET_DSA_TAG_8021Q
      code and leveraging it from our own CONFIG_NET_DSA_TAG_SJA1105.
      
      There are two types of traffic: regular and link-local.
      
      The link-local traffic received on the CPU port is trapped from the
      switch's regular forwarding decisions because it matched one of the two
      DMAC filters for management traffic.
      
      On transmission, the switch requires special massaging for these
      link-local frames. Due to a weird implementation of the switching IP, by
      default it drops link-local frames that originate on the CPU port.
      It needs to be told where to forward them to, through an SPI command
      ("management route") that is valid for only a single frame.
      So when we're sending link-local traffic, we are using the
      dsa_defer_xmit mechanism.
      Signed-off-by: default avatarVladimir Oltean <olteanv@gmail.com>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      227d07a0
  8. 03 May, 2019 1 commit