1. 27 Sep, 2019 1 commit
  2. 03 Aug, 2019 1 commit
    • Claudiu Manoil's avatar
      enetc: Add mdio bus driver for the PCIe MDIO endpoint · 231ece36
      Claudiu Manoil authored
      
      
      ENETC ports can manage the MDIO bus via local register
      interface.  However there's also a centralized way
      to manage the MDIO bus, via the MDIO PCIe endpoint
      device integrated by the same root complex that also
      integrates the ENETC ports (eth controllers).
      
      Depending on board design and use case, centralized
      access to MDIO may be better than using local ENETC
      port registers.  For instance, on the LS1028A QDS board
      where MDIO muxing is required.  Also, the LS1028A on-chip
      switch doesn't have a local MDIO register interface.
      
      The current patch registers the above PCIe endpoint as a
      separate MDIO bus and provides a driver for it by re-using
      the code used for local MDIO access.  It also allows the
      ENETC port PHYs to be managed by this driver if the local
      "mdio" node is missing from the ENETC port node.
      
      Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      231ece36
  3. 29 May, 2019 1 commit
  4. 24 May, 2019 1 commit
    • Y.b. Lu's avatar
      enetc: add hardware timestamping support · d3982312
      Y.b. Lu authored
      
      
      This patch is to add hardware timestamping support
      for ENETC. On Rx, timestamping is enabled for all
      frames. On Tx, we only instruct the hardware to
      timestamp the frames marked accordingly by the stack.
      
      Because the RX BD ring dynamic allocation has not been
      supported and it is too expensive to use extended RX BDs
      if timestamping is not used, a Kconfig option is used to
      enable extended RX BDs in order to support hardware
      timestamping. This option will be removed once RX BD
      ring dynamic allocation is implemented.
      
      Signed-off-by: default avatarYangbo Lu <yangbo.lu@nxp.com>
      Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      d3982312
  5. 15 May, 2019 1 commit
  6. 01 Mar, 2019 1 commit
  7. 25 Jan, 2019 3 commits
    • Claudiu Manoil's avatar
      enetc: Add RFS and RSS support · d382563f
      Claudiu Manoil authored
      
      
      A ternary match table is used for RFS. If multiple entries in the table
      match, the entry with the lowest numerical values index is chosen as the
      matching entry.  Entries in the table are identified using an index
      which takes a value from 0 to PRFSCAPR[NUM_RFS]-1 when accessed by the
      PSI (PF).
      Portions of the RFS table can be assigned to each SI by the PSI (PF)
      driver in PSIaRFSCFGR.  Assignments are cumulative, the entries assigned
      to SIn start after those assigned to SIn-1.  The total assignments to
      all SIs must be equal to or less than the number available to the port
      as found in PRFSCAPR.
      
      For RSS, the Toeplitz hash function used requires two inputs, a 40B
      random secret key that is supplied through the PRSSKR0-9 registers as well
      as the relevant pieces of the packet header (n-tuple).  The 6 LSB bits of
      the hash function result will then be used as a pointer to obtain the tag
      referenced in the 64 entry indirection table.  The result will provide a
      winning group which will be used to help route the received packet.
      
      Signed-off-by: default avatarAlex Marginean <alexandru.marginean@nxp.com>
      Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      d382563f
    • Claudiu Manoil's avatar
      enetc: Add vf to pf messaging support · beb74ac8
      Claudiu Manoil authored
      
      
      VSIs (VFs) may send a message to the PSI (PF) for general notification
      or to gain access to hardware resources which requires host inspection.
      These messages may vary in size and are handled as a partition copy
      between two memory regions owned by the respective participants.
      The PSI will respond with fail or success and a 16-bit message code.
      The patch implements the vf to pf messaging mechanism above and, as the
      first application making use of this support, it enables the VF to
      configure its own primary MAC address.
      
      Signed-off-by: default avatarCatalin Horghidan <catalin.horghidan@nxp.com>
      Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      beb74ac8
    • Claudiu Manoil's avatar
      enetc: Introduce basic PF and VF ENETC ethernet drivers · d4fd0404
      Claudiu Manoil authored
      
      
      ENETC is a multi-port virtualized Ethernet controller supporting GbE
      designs and Time-Sensitive Networking (TSN) functionality.
      ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
      Endpoint (RCIE).  As such, it contains multiple physical (PF) and
      virtual (VF) PCIe functions, discoverable by standard PCI Express.
      
      Introduce basic PF and VF ENETC ethernet drivers.  The PF has access to
      the ENETC Port registers and resources and makes the required privileged
      configurations for the underlying VF devices.  Common functionality is
      controlled through so called System Interface (SI) register blocks, PFs
      and VFs own a SI each.  Though SI register blocks are almost identical,
      there are a few privileged SI level controls that are accessible only to
      PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
      As such, the bulk of the code, including datapath processing, basic h/w
      offload support and generic pci related configuration, is shared between
      the 2 drivers and is factored out in common source files (i.e. enetc.c).
      
      Major functionalities included (for both drivers):
      MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
      to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
      jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
      support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
      initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
      CTAG filtering, VF mac address config support, VF VLAN isolation support,
      etc.
      
      Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      d4fd0404